Hitachi H8S/2645, Руководство по оборудованию

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6.1.3 Register Configuration
Table 6-1 shows the PC break controller registers.
Table 6-1 PC Break Controller Registers
Initial Value
Name Abbreviation R/W Reset Address
* 1
Break address register A BARA R/W H'XX000000 H'FE00
Break address register B BARB R/W H'XX000000 H'FE04
Break control register A BCRA R/(W)
* 2
H'00 H'FE08
Break control register B BCRB R/(W)
*
2
H'00 H'FE09
Module stop control register C MSTPCRC R/W H'FF H'FDEA
Notes:
*
1 Lower 16 bits of the address.
* 2 Only a 0 may be written to this bit to clear the flag.
6.2 Register Descriptions
6.2.1 Break Address Register A (BARA)
Bit
Initial value
Read/Write —
—
31
Unde-
fined
—
—
24
Unde-
fined
R/W
BAA
23
23
0
R/W
BAA
22
22
0
R/W
BAA
21
21
0
R/W
BAA
20
20
0
R/W
BAA
19
19
0
R/W
BAA
18
18
0
R/W
BAA
17
17
0
R/W
BAA
16
16
0
R/W
0
BAA
7
7
R/W
0
BAA
6
6
R/W
0
BAA
5
5
R/W
0
BAA
4
4
R/W
0
BAA
3
3
R/W
0
BAA
2
2
R/W
0
BAA
1
1
R/W
0
BAA
0
0
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
BARA is a 32-bit readable/writable register that specifies the channel A break address.
BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode.
Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.
Bits 23 to 0—Break Address A23 to A0 (BAA23–BAA0): These bits hold the channel A PC
break address.