Device Connections and Switches
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PC Cards cifX PCI, PCIe, Low Profile PCIe | Installation, Operation and Hardware Description
DOC120204UM46EN | Revision 46 | English | 2015-12 | Relelased | Public
© Hilscher, 2008-2015
9.8 SYNC Connector (Pin-Assignment, Hardware/Firmware)
9.8.1
Pin Assignment SYNC Connector, X51 (CIFX 50 50E 70E)
Only for:
CIFX 50-RE (from hardware Rev. 3 on), CIFX 50-RE\ET, CIFX 50E-RE,
CIFX 50E-RE\ET, CIFX 70E-RE
Pin
Signal
1
GND
2
IO_SYNC0
3
IO_SYNC1
Table 88: Pin Assignment for SYNC Connector, X51
9.8.2
Pin Assignment SYNC Connector, J1 (CIFX 100EH)
Only for: CIFX 100EH-RE\CUBE.
Pin
Signal
1
IO_SYNC0
2
Jumper set:
SYNC signal is transferred to the PCI Express Bus Pin B24*
Jumper not set:
static high 3.3 V (with pull-up)
3
IO_SYNC1
Table 89: Pin Assignment for SYNC Connector, J1
Note!
*
•
If the jumper is set on Pin1-Pin2, then the
IO_SYNC0
signal will be
transferred to the PCI Express Bus X2 (pin B24).
Or
•
If the jumper is set on Pin2-Pin3, then the
IO_SYNC1
signal will be
transferred to the PCI Express Bus X2 (pin B24).
Or
•
If the no jumper is set, then the signal at the PCI Express Bus X2 pin
B24 will be static High
3.3 V
(with pull-up).
Compare section
Pin Assignment for PCI Express Bus CIFX 100EH-
RE\CUBE
on page 115.
