Hal Communications DKB-2010, Инструкция по эксплуатации, Страница: 28 / 101

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As described in Section 4.7, the RTTY control circuit detects when a change of case is necessary. In this
instance, the shift register is disabled until after the case code has been transmitted. The register output
remains high during this period. Clock pulses are controlled by the logic circuit shown at the left in Figure
8.7.
The case-code character to be transmitted is selected by the NAND gates at the far left (parts of IC's 28
and 33). At the beginning of the character the INSERT CASE CODE line, coupled to one input of each gate,
goes high. If the letter-shift character is to be sent, the LTRS CASE bus goes high, enabling the lower gate.
The FIGS CASE line remains low, disabling the upper gate, so its output remains high. The
C = 0v1 signal
then appears, inverted, at the gate output, as shown in Figure 4.4.
Figure 4.4 Generation of the Letters - Shift Code
If, on the other hand, the figures-shift code is required, the FIGS CASE line is high, enabling the upper
gate. The LTRS CASE line is low, so that the lower gate is closed and its output remains high. Both the c =
0v1 and the C = 6v7 signals are coupled to inputs of the upper gate with the result that these signals are
logically added to produce the figures-shift character, as shown in Figure 4.5.
Figure 4.5 Generation of the Figures - Shift Code