GE Corometrics 170 Series, Руководство по обслуживанию

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5-24 170 Series Monitor Revision C
2000947-004
Theory of Operation: Main Board Theory of Operation
Recorder Interface Module
The recorder interface consists of motor control, paper status logic, and printhead
control logic. The motor control consists of latch U3, buffer U6, and FET transistors
Q5–Q8. The four phase signals are generated by the processor using U3. These
phases are translated to 5 V and buffered by U6 to drive the FETs which in turn
drive the unipolar motor. Clamp diodes are used to limit the inductive spike
generated when the switches open. The paper status logic consists of paper out and
paper misload optical sensor interface circuitry as well as a door switch interface.
The paper status logic consists of dual digital potentiometer U9, resistors R216 and
R217 for LED drive to the paper out sensor, and R219 and R220 for LED drive to
the paper misload sensor. The digital potentiometer connects to the collector of the
sensor transistor and becomes the variable pull-up. These signals (MISCOIL and
OUTCOIL) are further processed by the analog-to-digital converter to determine the
correct threshold for the two sensors. Clamp device U8 is used for ESD protection.
The door switch input is a switch closure to ground and is read by the processor
through buffer U15. The printhead interface consists of PAL U4 which contains the
printhead control latch, head protection circuitry, and printhead shift register. The
printhead control latch contains the four strobes for the printhead sections, the
printhead load line, and the printhead power supply enable line. The printhead
protection timer consists of a four-bit counter which uses a 2 kHz clock [Usmode,
U4 (pin 35)] to count off six clocks. The counter is enabled when any one of the
four processor-latched strobes is active. After six counts of any active strobe (3 ms),
the counter disables all four output strobes and turns off the +24 V head supply. The
circuit resets when the processor-latched strobes return to an inactive state. The
power fail control line input U4 (pin 76) is also a form of protection which turns off
all strobes and the power supply when the +12 V drops to about 10 V. The
printhead shift register consists of an 8-bit shift register which clocks out D7 first
and clock counters which allow eight clocks to be output for every processor write
to the register. The clock counter also provides a done status bit (BUSY*) which
goes high after all eight bits are shifted out. This status bit is read through the
UART spare port line U21 (pin 28).
Figure 5-16 provides a block diagram of the recorder interface.