GE Corometrics 170 Series, Руководство по обслуживанию

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5-20 170 Series Monitor Revision C
2000947-004
Theory of Operation: Main Board Theory of Operation
The processor (U1) is an Hitachi SH3 used with a 32-bit data bus and 24-bit address
bus. Series 100
Ω
resistors and 100 k
Ω
pull-up resistors are provided for all
address, data bus and output lines. The series resistors limit transient response
resulting in better EMI performance. Pull-up resistors prevent these lines from
floating if the processor enters sleep mode which tri-states these lines. Crystal X2 is
the main crystal for the processor running at 12.288 MHz. Mode lines which the
CPU examines at power up are pulled up and down to set the CPU to mode 4. This
allows the CPU to run internally at either X2 x 1 (12.288 MHz) or X2 x 4 (49.152
MHz). The external bus and SYSCLK run at the X1 frequency. Crystal X1 is for the
processor’s real-time clock. The real-time clock is not used; however, in addition to
time/date, it can be used to process interrupts for exiting sleep mode. A MAX809
reset IC (U2) monitors 3 V backup power to hold RESET* low during power up
from the AC line cord and or the DC power cable. Power-up reset using the power
button is accomplished through an external RC circuit (R544 and C285) for a
shorter on reset time.
Four AMD AM29LV800B 8 Mb flash memory parts (U23–U26) are used to provide
4 MB of data storage and non-volatile program memory. The flash parts are
arranged in pairs to allow 32-bit data access. Separate write enable lines allow
access to individual 16-bit words, if required. Chip selects for each flash pair are
controlled by the programmable array logic device (PAL) U4 and are memory
mapped to make all 4 MB appear as a single area of memory.
The system RAM consists of two Hitachi HM5216165 16-Mb SDRAMs (U27,
U28). The processor provides all of the DRAM support signals (RAS, CAS, etc.).
A 32-bit data bus is used and 8- and 16-bit access are supported.
An AT29LV010A 1 Mb flash memory part (U29) is used as a boot ROM. The
processor begins execution from this area of memory (Area 0 / CS0*). An 8-bit data
bus is used.
A battery RAM, with real-time clock MT48T18 (U31), provides the clock and 8k x
8 data storage function for parameters, error logs, etc. Transceiver U30 buffers and
voltage translates data from the 5 V battery RAM.
The PAL (U4) provides the address decoding for the system flash memory, UART,
battery RAM, display, input buffers, and recorder control latches. The PAL also
contains latches which allow control of the printhead, serial peripheral interface
(SPI) chip selects, telemetry, and fetal movement signal controls. PAL U4 also
provides the parallel-to-serial conversion for the printhead data. The PFAIL and
software enable bits are used to disable battery RAM writes.
Figure 5-12 provides a
block diagram of the PAL.