Freescale Semiconductor Symphony DSP56724, Справочное руководство

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S/PDIF—Sony/Philips Digital Interface
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor 18-15
18.3 S/PDIF Receiver
The S/PDIF receiver extracts the audio data from each S/PDIF frame and places the data in a 6-deep FIFO.
The channel status and user bits are also extracted from each frame and placed in corresponding registers.
The S/PDIF receiver also provides a bypass option for direct transfer of the S/PDIF input signal to the
S/PDIF transmitter.
The S/PDIF receiver handles the main data audio stream and recovers the bit clock from the S/PDIF input
signal. The sample rate can be determined from the frequency measuring block. Additionally, the receiver
supports the S/PDIF C and U channels. The S/PDIF C and U channel data is interfaced directly to
memory-mapped registers. The input data is sent via a 6-deep FIFO to the memory-mapped data registers.
All the data registers are controlled by the Interrupt Control Block and transferred to the memory-mapped
IP bus.
The following functions are performed by the S/PDIF receiver:
• Audio Data Reception— see Section 18.3.1, “Audio Data Reception ”
• Channel Status bits Reception— see Section 18.3.2, “Channel Status Reception ”
• User Channel bits Reception— see Section 18.3.3, “User Bit Reception ”
• Validity Flag Reception— see Section 18.3.4, “Validity Flag Reception ”
• S/PDIF Receiver Exception support— see Section 18.3.5, “S/PDIF Receiver Interrupt Exception
Definition ”
• S/PDIF Lock Detection
18.3.1 Audio Data Reception
The S/PDIF Receiver block extracts the audio data from the IEC958 stream, and outputs this via a 6-deep
FIFO to the memory-mapped registers SPDIFRcvLeft and SPDIFRcvRight. Data from the S/PDIF
receiver is buffered in the receive FIFO, and can be read by any DSP Core from the memory-mapped
registers.
a) S/PDIF Receiver Data Registers - Behavior on Overrun and Underrun
The S/PDIF Data Receive registers (SPDIFRcvLeft and SPDIFRcvRight) have different FIFOs
for the left and right channels. As a result, there is always the possibility that the left and right
FIFOs may go out of sync due to FIFO underruns and overruns that affect only one part (left
or right) of any FIFO. To prevent this from happening, two mechanisms to prevent mismatch
between the FIFOs are available:
7 Reserved Returns zero when read.
6–0 TxClk_DF Divider factor (1-128)
4’d0 divider factor is 1
4’d1 divider factor is 2
...
4’d127 divider factor is 128
Table 18-20. SPDIFTxClk Register (STC) Fields (Continued)
Bit Field Description