Inter-Core Communication (ICC)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
13-7
13.2.2.4
ICCR2 (ICC Control Register 2)
The ICCR2 control register is show in
Address
Y:FFFFD9
Access: User Read
23
22
21
20
19
18
17
16
15
14
13
12
R
Communication Data
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
R
Communication Data
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-5. ICDR2 Data Register
Table 13-5. ICDR2 Field Descriptions
Bit
Field Description
23–0
Communication Data
Read-only communication data reflecting the other core’s ICDR1 data register.
Address
Y:FFFFD8
Access: User Read
23
22
21
20
19
18
17
16
15
14
13
12
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
R
DRE
IF
W
Reset
0
0
0
0
0
0
0
0
0
1
0
0
Figure 13-6. ICCR2 Control Register
Table 13-6. ICCR2 Field Descriptions
Bit
Field Description
23–3
Reserved
Read-only
2
DRE
Data Register Empty flag that reflects the status of the same bit of the other core’s ICCR1 register.
1
IF
Interrupt Flag that reflects the status of the same bit of the other core’s ICCR1 register.
1: Interrupt Flag is set valid, and interrupt is pending.
0: Interrupt Flag is cleared, no interrupt is pending.
0
Reserved
Read-only
Содержание Symphony DSP56724
Страница 22: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 1 10 Freescale Semiconductor Introduction ...
Страница 52: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 2 30 Freescale Semiconductor Signal Descriptions ...
Страница 112: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 7 12 Freescale Semiconductor Clock Generation Module CGM ...
Страница 244: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 14 6 Freescale Semiconductor Shared Bus Arbiter ...
Страница 246: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 15 2 Freescale Semiconductor Shared Memory Shared Memory ...