Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
2-10
Freescale Semiconductor
Signal Descriptions
Table 2-11. Serial Host Interface Signals (SHI)
Signal
Name
Signal Type
State
During
Reset
Description
SCK
Input or
Output
Tri-stated
SPI Serial Clock
When the SPI is configured as a master, the SCK signal is an output; when the SPI
is configured as a slave, the SCK signal is a Schmitt-trigger input.
When the SPI is configured as a master, the SCK signal is derived from the internal
SHI clock generator.
When the SPI is configured as a slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the data transfer. The SCK signal is
ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not
asserted.
In both the master and slave SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge where data is stable. Edge polarity is
determined by the SPI transfer protocol.
SCL
Input or
Output
I
2
C Serial Clock
SCL carries the clock for I
2
C bus transactions in the I
2
C mode. When the SPI is
configured as a master, SCL is an open-drain output; when the SPI is configured as
a slave, SCL is a Schmitt-trigger input.
SCL should be connected to V
DD
through a pull-up resistor.
This signal is tri-stated during hardware, software and individual reset. Thus, there
is no need for an external pull-up in this state.
This pin is shared by SHI and SHI_1 in DSP56725 80-pin and DSP56724 144-pin
packages.
Uses an internal pull-up resistor.
MISO
Input or
Output
Tri-stated
SPI Master-In-Slave-Out
When the SPI is configured as a master, MISO is the master data input line. The
MISO signal is used in conjunction with the MOSI signal for transmitting and
receiving serial data.
When the SPI is configured as a master, MISO is a Schmitt-trigger input; when the
SPI is configured as a slave, MISO is an output, and is tri-stated when SS is
deasserted.
An external pull-up resistor is not required for SPI operation.
SDA
Input or
Open-drain
Output
I
2
C Data and Acknowledge
In I
2
C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output
when transmitting. SDA should be connected to V
DD
through a pull-up resistor.
SDA carries the data for I
2
C transactions. The data in SDA must be stable during the
high period of SCL. The data in SDA is only allowed to change when SCL is low.
When the bus is free, SDA is high.
In start and stop events, the SDA line is only allowed to change during the time SCL
is high.
A start event is a high-to-low transition of the SDA line while SCL is high. A stop event
is a low-to-high transition of SDA while SCL is high.
This signal is tri-stated during hardware, software and individual reset. Thus, there
is no need for an external pull-up in this state.
This pin is shared by SHI and SHI_1 in DSP56725 80-pin and DSP56724 144-pin
packages.
Uses an internal pull-up resistor.
Содержание Symphony DSP56724
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Страница 52: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 2 30 Freescale Semiconductor Signal Descriptions ...
Страница 112: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 7 12 Freescale Semiconductor Clock Generation Module CGM ...
Страница 244: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 14 6 Freescale Semiconductor Shared Bus Arbiter ...
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