Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
19-24
Freescale Semiconductor
Asynchronous Sample Rate Converter
Figure 19-16. Memory Access Data Register (ASRMAD)
When ASRMAA:MEMOPT[1:0] = 11; it means the accessing ASRMAD will actually be accessing the
small internal register bank. Currently this small register bank includes only two 14-bit registers (Register
0, Register 1):
•
Register 0: TS76KHZ[13:0]: Read/Write. This value should be equal to Fsys (frequency of the
system clock, in Hz)/76000. The reset value is $0A47, which assumes that Fsys = 200 MHz.
•
Register 1: TS56KHZ[13:0]: Read/Write. This value should be equal to Fsys (frequency of the
system clock, in Hz)/56000. The reset value is $0DF3, which assumes that Fsys = 200 MHz.
These two small internal register bank registers help the ASRC internal logic decide the pre-processing
and the post-processing options automatically (see
). To access these two
registers, first assign $C00000h to ASRMAA, then:
1. Read the ASRMAD register, which will give the value of TS76KHZ[13:0];
then read the ASRMAD register again, which will give the value of TS56KHZ[13:0].
2. Write the ASRMAD register, to assign a value to TS76KHZ[13:0];
then write the ASRMAD register again, to assign a value to TS56KHZ[13:0].
Offset 0xD
Access: User Read/Write
23
22
21
20
19
18
17
16
15
14
13
12
R
DATA[23:12]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
R
DATA[11:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Table 19-15. Memory Access Address Register (ASRMAA)
Bit
Field
Description
23–22
MEMOPT
Chooses which part of the memory to read/write.
00 X memory
01 Y memory, this case is only supported when ASRC is not enabled.
11 Internal register banks.
10 Reserved
21–13
Reserved. Should be written as zero for compatibility.
12–0
ADDR
Selects the address for read/write.
Every read/write operation through ASRMAD will increase the address by 1; the updated address is
readable through this register.
Содержание Symphony DSP56724
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