Signal Descriptions
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
2-5
2.2
Signals in Each Functional Group
2.2.1
Power
2.2.2
Ground
Table 2-3. Power Pins
Power Name
Description
PLLA_VDD
PLLP_VDD
PLLA1_VDD
PLLP1_VDD
PLL Power
The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 3.3 V
DD
power rail. The user must provide adequate external decoupling capacitors.
PLLD_VDD
PLLD1_VDD
PLL Power
The voltage (1.0 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 1.0 V
DD
power rail. The user must provide adequate external decoupling capacitors.
CORE_VDD
Core Power
The voltage (1.0 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 1.0 V
DD
power rail. The user must provide adequate decoupling capacitors.
IO_VDD
I/O Power
The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 3.3 V
DD
power rail. This is an isolated power for the SHI, SHI_1, ESAI, ESAI_1, ESAI_2, ESAI_3,
Timer I/O, and other IO signals. The user must provide adequate external decoupling capacitors.
Table 2-4. Ground Pins
Ground Name
Description
PLLA_GND
PLLP_GND
PLLA1_GND
PLLP1_GND
PLL Ground
The PLL ground should be provided with an extremely low-impedance path
to
ground. The user must provide
adequate external decoupling capacitors.
PLLD_GND
PLLD1_GND
PLL Ground
The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide
adequate external decoupling capacitors.
CORE_GND
Core Ground
The Core ground should be provided with an extremely low-impedance path to ground. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
IO_GND
I/O Ground
IO_GND is an isolated ground for the SHIs, ESAIs, Timer I/O and LIBU IO. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
GND
Ground
This connection must be tied externally to all other chip ground connections. The user must provide adequate
external decoupling capacitors.
Содержание Symphony DSP56724
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Страница 52: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 2 30 Freescale Semiconductor Signal Descriptions ...
Страница 112: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 7 12 Freescale Semiconductor Clock Generation Module CGM ...
Страница 244: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 14 6 Freescale Semiconductor Shared Bus Arbiter ...
Страница 246: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 15 2 Freescale Semiconductor Shared Memory Shared Memory ...