Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
9-14
Freescale Semiconductor
Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)
Hardware and software reset clear all the bits in the TCR register.
9.2.2.1
TCR ESAI Transmit 0 Enable (TE0)—Bit 0
TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set and a frame
sync is detected, the transmit #0 portion of the ESAI is enabled for that frame. When TE0 is cleared, the
transmitter #0 is disabled after completing transmission of data currently in the ESAI transmit shift
register. The SDO0 output is tri-stated, and any data present in TX0 is not transmitted, that is, data can be
written to TX0 with TE0 cleared, but data is not transferred to the transmit shift register #0.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE0 and setting it again disables the transmitter #0 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO0 pin remains in the high-impedance state.The on-demand mode transmit enable sequence
can be the same as the normal mode, or TE0 can be left enabled.
9.2.2.2
TCR ESAI Transmit 1 Enable (TE1)—Bit 1
TE1 enables the transfer of data from TX1 to the transmit shift register #1. When TE1 is set and a frame
sync is detected, the transmit #1 portion of the ESAI is enabled for that frame. When TE1 is cleared, the
transmitter #1 is disabled after completing transmission of data currently in the ESAI transmit shift
register. The SDO1 output is tri-stated, and any data present in TX1 is not transmitted, that is, data can be
written to TX1 with TE1 cleared, but data is not transferred to the transmit shift register #1.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence
can be the same as the normal mode, or TE1 can be left enabled.
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB5
TSWS1 TSWS0 TMOD1 TMOD0 TWA
TSHFD
TE5
TE4
TE3
TE2
TE1
TE0
23
22
21
20
19
18
17
16
15
14
13
12
TLIE
TIE
TEDIE
TEIE
TPR
PADC
TFSR
TFSL TSWS4 TSWS3 TSWS2
Reserved bit—read as zero; should be written with zero for future compatibility.
Figure 9-5. TCR Register
Содержание Symphony DSP56724
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Страница 52: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 2 30 Freescale Semiconductor Signal Descriptions ...
Страница 112: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 7 12 Freescale Semiconductor Clock Generation Module CGM ...
Страница 244: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 14 6 Freescale Semiconductor Shared Bus Arbiter ...
Страница 246: ...Symphony DSP56724 DSP56725 Multi Core Audio Processors Rev 0 15 2 Freescale Semiconductor Shared Memory Shared Memory ...