Freescale Semiconductor Symphony DSP56724, Справочное руководство

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External Memory Controller (EMC)
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor 21-17
14–13 XAM Extended address mask. Masks the corresponding XBA bits in the BRx register. For example, if
BRx[XBA] = 00 or 01, and ORx[XAM] = 10, then the settings permit access from both X and Y.
12 BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
11–9 — Reserved
8 BI Burst inhibit. Indicates if this memory bank supports burst accesses.
0 The bank supports burst accesses.
1 The bank does not support burst accesses. The selected UPM executes burst accesses as a series
of single accesses.
7–3 — Reserved
2 TRLX Timing relaxed. Works in conjunction with EHTR to extend hold time on read accesses.
1 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a
read access from the current bank and the next access.
TRLX EHTR Meaning
0 0 Normal timing is generated by the memory controller. No additional cycles are
inserted.
0 1 1 idle clock cycle is inserted.
1 0 4 idle clock cycles are inserted.
1 1 8 idle clock cycles are inserted.
0 EAD External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles. (LALE is asserted for one bus clock cycle only.)
1 Extra bus clock cycles are added. (LALE is asserted for the number of bus clock cycles specified
by CRR[EADC].)
Table 21-16. ORL x
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UPM Field Descriptions (Continued)
Bits Name Description