Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-90 Freescale Semiconductor
The result format and calibration submodule formats the returning data into result messages and sends
them to the RFIFOs. The returning data can be data read from an ADC register, a conversion result, or a
time stamp. The formatting and calibration of conversion results also take place inside this submodule.
The time stamp logic latches the value of the time base counter when detecting the end of the analog input
voltage sampling, and sends it to the result format and calibration submodule as time stamp information.
The MUX control logic generates the proper MUX control signals and, when the ADC0/1_EMUX bits are
asserted, the MA signals based on the channel numbers extracted from the ADC Command.
ADC commands are stored in the ADC command buffers (2 entries) as they come in and they are executed
on a first-in-first-out basis. After the execution of a command in ENTRY1 finishes, all commands are
shifted one entry. After the shift, ENTRY0 is always empty and ready to receive a new command.
Execution of configuration commands only starts when they reach ENTRY1. Consecutive conversion
commands are pipelined, and their execution can start while in ENTRY0. This is explained below.
A/D conversion accuracy can be affected by the settling time of the input channel multiplexers. Some time
is required for the channel multiplexer’s internal capacitances to settle after the channel number is
changed. If the time prior to and during sampling is not long enough to permit this settling, then the voltage
on the sample capacitors will not accurately represent the voltage to be read. This is a problem in particular
when external muxes are used.
To maximize settling time, when a conversion command is in buffer ENTRY1 and another conversion
command is identified in ENTRY0, then the channel number of ENTRY0 is sent to the
MUX control logic
half an ADC clock before the start of the sampling phase of the command in ENTRY0. This pipelining of
sample and settling phase is shown in
Figure 19-52 (b).
This provides more accurate sampling, which is specially important for applications that require high
conversion speeds, i.e., with the ADC running at maximum clock frequency and with the analog input
voltage sampling time set to a minimum (2 ADC clock cycles). In this case the short sampling time may
not allow the multiplexers to completely settle. The second advantage of pipelining conversion commands
is to provide equal conversion intervals even though the sample time increases on second and subsequent
conversions. See
Figure 19-52 . This is important for any digital signal process application.