Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 15-7
• Incorporated review comments:
Section 15.6, “SRAM ECC Mechanism added the following paragraph
The SRAM ECC detects the following conditions and produces the following results:
Detects and corrects all 1-bit errors
Detects and flags all 2-bit errors as non-correctable errors
Detects 72-bit reads (64-bit data bus plus the 8-bit ECC) that return all zeros or all ones, asserts an error indicator on the
bus cycle, and sets the multiple-bit error flag
SRAM does not detect all errors greater than 2-bits.
• Changed “the ECC is merged with” to “the ECC is appended to the” throughout this section
Rewrote ECC process:
FROM:
The ECC bits are then merged with the data segment and written to SRAM.
If the write operation is less than the entire 64-bit data width (1-, 2-, or 4-byte
segment), the following occurs:
-- The ECC checks the entire 64-bits for errors. Hardware corrects single-bit errors
and flags double-bit errors. Bit errors greater than 2 bits are flagged as multiple-bit
errors.
-- The write data-bytes (1-, 2-, or 4-byte segment) and the ECC bits are merged with
the original 64-bit data.
-- The ECC bits are then calculated on the new 64-bit data field.
-- The entire 8-bytes and the new ECC bits are written to SRAM.
TO:
The 8-bit ECC is appended to the data segment and written to SRAM.
If the write operation is less than the entire 64-bit data width (1-, 2-, or 4-byte segment), the following occurs:
1. The ECC mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or flagging errors.
2. The write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64-bits on the data bus.
3. The ECC is then calculated on the resulting 64-bits formed in the previous step.
4. The 8-bit ECC result is appended to the 64-bits from the data bus, and the 72-bit value is then written to SRAM.
Changed
Section 15.6.1, “Access Timing from:
Table 15-2 shows the wait states for accesses, column Current is the access
being measured, and column Previous is the RAM access during the previous clock.
To: Table 15-2 lists the various combinations of read and write operations to SRAM and the number of wait states used for the
each operation. The table columns contain the following information:
Current Access Lists the access operations to SRAM
Previous Access Lists the access operations that can precede the current access to SRAM
(access operation during the previous clock)
Wait States Lists the number of wait states (bus clocks) used by the access operation according to the
combination of the current and previous access operation
• Changed Table 15-2 to include rows 2 through 5 from the Read section in the Burst Read section. Burst read wait state
values used are: Pipelined Read 1,0,0,0;
Burst Read 1,0,0,0; 64-bit Write 2.0.0.0; 8/16/32-bit write 0,0,0,0 (read from the same address) and 1,0,0,0 (read from a
different address).
• Changed ‘insure’ to ‘ensure’ and removed future tense
These review changes continue in next row.
Table 15-3. Changes to MPC5553/5554RM for Rev. 4.0 Release (Continued)