Freescale Semiconductor MPC5553, Справочное руководство

Страница: 753 / 1208

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
18-46 Freescale Semiconductor
18.6 Initialization/Application Information
After initial power-on reset, the eTPU remains in an idle state (except when debug is asserted on
power-on reset—in this case, the microengines awakens in halt state). In addition, the SCM should
be initialized with the eTPU application prior to configuring the eTPU.
18.7 Revision History
Table 18-29. Changes to MPC5553/5554 RM for Rev. 4.0 Release
Description of Change
• In Section 18.1.3, “eTPU Operation Overview ”, changed:
FROM: “A thread may be interrupted only by resetting the entire eTPU module.”
TO: “The core may terminate the thread by writing 1 to the FEND
bit in the ETPUECR register.”
• In Section 18.1.3.1.1, “Time Bases ” removed the words “or be driven by” from the sentence
“The TCRs may also drive or be driven by an eMIOS time base through the shared time and counter (STAC) bus, or they
may be written by eTPU function software.” It now reads ““The TCRs may also drive an eMIOS time base through the
shared time and counter (STAC) bus, or they may be written by eTPU function software.”
• Figure 18-3: changed title from SDM Write to SDM PSE Area Write.
• In
Section 18.1.4, “Features ” changed:
FROM: “The first time base may be clocked by the system clock with programmable prescaler division from 2 to 512 (in
steps of 2), or by the output of the second time base prescaler.”
TO: “The first time base may be clocked by the system clock with programmable prescaler division from 2 to 512 (in steps
of 2)
• In Section 18.1.4, “Features ” added this bullet:
“The second time base has a programmable prescaler that applies to all TCR2 clock inputs except the angle counter.”
• In Section 18.1.4, “Features ” changed:
FROM: “32-bit microengine registers and 24-bit resolution ALU, with 1 microcycle addition and subtraction, absolute
value, bitwise logical operations on 24-bit, 16-bit, or byte operands: single bit manipulation, shift operations, sign
extension and conditional execution.”
TO: “24-bit registers and ALU, plus one 32-bit register for full-width SDM access”
• In Section 18.1.4, “Features ” added these bullets:
--Hardware breakpoints on data access, qualified by address and/or data values.
-- Hardware breakpoints on instruction address.
• In Section 18.3.1, “Overview ” corrected the number of external signals to 65 from 69. The four output disable input signals
are now designated as internal signals.
• Changed wording in SCMMISF bit:
FROM: “This bit is automatically cleared when SCMMISEN changes from 0 to 1, or when global exception is cleared by
writing 1 to GEC.”
TO: "This bit is cleared by writing 1 to GEC".
• In Section 18.4.2.1.4, “eTPU SCM Off-Range Data Register (ETPU_SCMOFFDATAR) ” added a NOTE
• In Section 18.4.2.1.5, “eTPU Engine Configuration Register (ETPU_ECR) ” in the MDIS bit, changed the Note to read:
TO: “After MDIS has been switched from 1 to 0 or vice-versa, do not switch its value again until STF switches to the same
value.”
• In Section 18.4.2.1.5, “eTPU Engine Configuration Register (ETPU_ECR) ” in the STF bit
removed the words “or after the STAC but stop has been asserted” from the STF bit description.
• In Table 18-12 , “ETPU_TBR Field Descriptions, in the TCR2CTL field, removed the phrase
“TCR2 can also be clocked by an internal peripheral timebase signal” and changed TCR2CTL=101 to “Reserved.”