Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
3-22 Freescale Semiconductor
Figure 3-14. Cache Organization and Line Format
3.3.2.2 Cache Lookup
After it is enabled, the unified cache will be searched for a tag match on all instruction fetches and data
accesses from the CPU. If a match is found, the cached data is forwarded on a read access to the instruction
fetch unit or the load/store unit (data access), or is updated on a write access, and may also be
written-through to memory if required.
When a read miss occurs, if there is a TLB hit and the cache inhibit bit (WIMGE=0bx0xxx) of the hitting
TLB entry is clear, the translated physical address is used to fetch a four doubleword cache line beginning
with the requested doubleword (critical doubleword first). The line is fetched and placed into the
appropriate cache block and the critical doubleword is forwarded to the CPU. Subsequent doublewords
may be streamed to the CPU if they have been requested and streaming is enabled via the DSTRM bit in
the L1CSR0 register.
During a cache line fill, doublewords received from the bus are placed into a cache linefill buffer, and may
be forwarded (streamed) to the CPU if such a request is pending. Accesses from the CPU following
delivery of the critical doubleword may be satisfied from the cache (hit under fill, non-blocking) or from
the linefill buffer if the requested information has been already received.
The cache always fills an entire line, thereby providing validity on a line-by-line basis. A cache line is
always in one of the following states: invalid, valid, or dirty (and valid). For invalid lines, the V bit is clear,
causing the cache line to be ignored during lookups. Valid lines have their V bit set and D bit cleared,
indicating the line contains valid data consistent with memory. Dirty cache lines have the D and V bits set,
indicating that the line has valid entries that have not been written to memory. In addition, a cache line may
be locked (L bit set) indicating the line is not available for replacement.
The cache should be explicitly invalidated after a hardware reset; reset does not invalidate the cache lines.
Following initial power-up, the cache contents will be undefined. The L, D and V bits may be set on some
lines, necessitating the invalidation of the cache by software before being enabled.
Way 0 Way 1 Way 2 Way 7
Line
•
•
•
•
•
•
•
•
•
•
•
•
V D Tag
Cache Line Format
Doubleword 3 Doubleword 2
Doubleword 1
Doubleword 0
Set 0
Set 1
Set 126
Set 127
•
•
•
L
A[0:19]
Tag address
Tag
V D
Valid
L
Line
Lock Line
Dirty
• • • •
Cache Tag Format
P
Parity
Bits
P
Note: Ways 2-7 available only in MPC5554