Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
10-14 Freescale Semiconductor
10.3.1.5 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0 – INTC_SSCIR7)
The INTC_SSCIR n support the setting or clearing of software settable interrupt requests. These registers
contain eight independent sets of bits to set and clear a corresponding flag bit by software. With the
exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. This
flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. Writing a 1
to SET
n will leave SET n unchanged at 0 but will set CLR n . Writing a 0 to SET n will have no effect. CLR n
is the flag bit. Writing a 1 to CLR n will clear it. Writing a 0 to CLR n will have no effect. If a 1 is written
to a pair SET n and CLR n bits at the same time, CLR n will be asserted, regardless of whether CLR n was
asserted before the write.
Although INTC_SSCI n is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided
that the access does not cross a 32-bit boundary.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg Addr Base + 0x0018
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg Addr Base + 0x0018
Figure 10-11. INTC End-of-Interrupt Register (INTC_EOIR)
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 CLRn
W SETn
Reset 0 0 0 0 0 0 0 0
Reg Addr Base + n
Figure 10-12. INTC Software Set/Clear Interrupt Register 0–7
(INTC_SSCIR0–INTC_SSCIR7)