Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-5
3.1.3.6 BIU Features
The features of the e200z6 BIU are as follows:
• 32-bit address bus plus attributes and control
• Separate unidirectional 64-bit read data bus and 64-bit write data bus
• Overlapped, in-order accesses
3.1.4 Microarchitecture Summary
The e200z6 processor utilizes a seven stage pipeline for instruction execution. The instruction fetch 1,
instruction fetch 2, instruction decode/register file read, execute1, execute2/memory access1,
execute3/memory access2, and register writeback stages operate in an overlapped fashion, allowing single
clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit arithmetic unit (AU), a logic unit (LU), a 32-bit barrel shifter
(shifter), a mask-insertion unit (MIU), a condition register manipulation unit (CRU), a count-leading-zeros
unit (CLZ), a 32x32 hardware multiplier array, result feed-forward hardware, and support hardware for
division.
Most arithmetic and logical operations are executed in a single cycle with the exception of multiply, which
is implemented with a pipelined hardware array, and the divide instructions. A count-leading-zeros unit
operates in a single clock cycle.
The instruction unit contains a PC incrementer and a dedicated branch address adder to minimize delays
during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions
into the execution pipeline. Branch target prefetching is performed to accelerate taken branches.
Prefetched instructions are placed into an instruction buffer capable of holding 6 sequential instructions.
Branch target addresses are calculated in parallel with branch instruction decode, resulting in execution
time of three clocks. Conditional branches which are not taken execute in a single clock. Branches with
successful lookahead and target prefetching have an effective execution time of one clock.
Memory load and store operations are provided for byte, halfword, word (32-bit), and doubleword data
with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of
data. These instructions can be pipelined to allow effective single cycle throughput. Load and store
multiple word instructions allow low overhead context save and restore operations. The load/store unit
contains a dedicated effective address adder to allow effective address generation to be optimized.
The condition register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture embedded category. The condition register consists of eight 4-bit fields that
reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and
logical instructions, and provide a mechanism for testing and branching.
Vectored and auto-vectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
The SPE APU supports vector instructions operating on 16- and 32-bit fixed-point data types, as well as
32-bit IEEE-754 single-precision floating-point formats, and supports single-precision floating-point
operations in a pipelined fashion. The 64-bit general-purpose register file is used for source and destination
operands, and there is a unified storage model for single-precision floating-point data types of 32-bits and
the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, divide,
compare, and conversion operations are provided, and most operations can be pipelined.