Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 19-21
19.3.2.8 eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)
The EQADC_FISRs contain flag and status bits for each CFIFO and RFIFO pair. Writing 1 to a flag bit
clears it. Writing 0 has no effect. Status bits are read only. These bits indicate the status of the FIFO itself.
5 — Reserved.
6 CFFEn CFIFO fill enable n. Enables the eQADC to generate an interrupt request (CFFSn is
asserted) or eDMA request (CFFSn is negated) when CFFFn in EQADC_FISRn (Section
19.3.2.8
)
is asserted.
0 Disable CFIFO fill eDMA or interrupt request
1 Enable CFIFO fill eDMA or interrupt request
Note: CFFEn must not be negated while an eDMA transaction is in progress.
7 CFFSn CFIFO fill select n. Selects if an eDMA or interrupt request is generated when CFFFn in
EQADC_FISRn (See Section 19.3.2.8
)
is asserted. If CFFEn is asserted, the eQADC
generates an interrupt request when CFFSn is negated, or it generates an eDMA request
if CFFSn is asserted.
0 Generate interrupt request to move data from the system memory to CFIFOn.
1 Generate eDMA request to move data from the system memory to CFIFOn.
Note: CFFSn must not be negated while an eDMA transaction is in progress.
8–11 — Reserved.
12 RFOIEn RFIFO overflow interrupt enable n. Enables the eQADC to generate an interrupt request
when the corresponding RFOFn in EQADC_FISRn (See Section 19.3.2.8
)
is asserted.
Apart from generating an independent interrupt request for an RFIFOn overflow event, the
eQADC also provides a combined interrupt at which the result FIFO overflow Interrupt, the
command FIFO underflow interrupt, and the command FIFO trigger overrun interrupt
requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and TORIEn are all asserted,
this combined interrupt request is asserted whenever one of the following 18 flags
becomes asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are
enabled). See
Section 19.4.7, “eQADC eDMA/Interrupt Request ,” for details.
0 Disable overflow interrupt request
1 Enable overflow Interrupt request
13 — Reserved.
14 RFDEn RFIFO drain enable n. Enables the eQADC to generate an interrupt request (RFDSn is
asserted) or eDMA request (RFDSn is negated) when RFDFn in EQADC_FISRn (See
Section 19.3.2.8
)
is asserted.
0 Disable RFIFO drain eDMA or interrupt request
1 Enable RFIFO drain eDMA or interrupt request
Note: RFDEn must not be negated while an eDMA transaction is in progress.
15 RFDSn RFIFO drain select n. Selects if an eDMA or interrupt request is generated when RFDFn
in EQADC_FISRn (See Section 19.3.2.8
)
is asserted. If RFDEn is asserted, the eQADC
generates an interrupt request when RFDSn is negated, or it generates an eDMA request
when RFDSn is asserted.
0 Generate interrupt request to move data from RFIFn to the system memory
1 Generate eDMA request to move data from RFIFOn to the system memory
Note: RFDSn must not be negated while an eDMA transaction is in progress.
Table 19-11. EQADC_IDCRn Field Descriptions (Continued)
Bits Name Description