Freescale Semiconductor MPC5553, Справочное руководство

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 11-23
Complete details for configuring the programmable frequency modulation is given in Section 11.4.3.2,
“Programming System Clock Frequency with Frequency Modulation .”
11.4.2.4 FMPLL Lock Detection
A pair of counters monitor the reference and feedback clocks to determine when the system has acquired
frequency lock. After the FMPLL has locked, the counters continue to monitor the reference and feedback
clocks and will report if/when the FMPLL has lost lock. The FMPLL_SYNCR provides the flexibility to
select whether to generate an interrupt, assert system reset, or do nothing in the event that the FMPLL loses
lock. See
Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR) for details.
When the frequency modulation is enabled, the loss of lock continues to function as described but with the
lock and loss of lock criteria reduced to ensure that false loss of lock conditions are not detected.
In bypass mode, the FMPLL cannot lock because the FMPLL is disabled.
11.4.2.5 FMPLL Loss-of-Lock Conditions
After the FMPLL acquires lock after reset, the FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS]
status bits are set. If the MFD is changed or if an unexpected loss of lock condition occurs, the LOCK and
LOCKS status bits are negated.
While the FMPLL is in an unlocked condition, the system clocks continue
to be sourced from the FMPLL as the FMPLL attempts to re-lock. Consequently, during the re-locking
process, the system clock frequency is not well defined and may exceed the maximum system frequency
thereby violating the system clock timing specifications (when changing MFD and PREDIV, this is
avoided by following the procedure detailed in
Section 11.4.3, “Clock Configuration ”). Because this
condition can arise during unexpected loss of lock events, it is recommended to use the loss of lock reset
functionality, see
Section 11.4.2.5.1, “FMPLL Loss-of-Lock Reset ,” below. However, LOLRE must be
cleared while changing the MFD otherwise a reset will occur.
After the FMPLL has relocked, the LOCK bit is set. The LOCKS bit remains cleared if the loss of lock
was unexpected. The LOCKS bit is set to 1 when the loss of lock was caused by changing the MFD.
11.4.2.5.1 FMPLL Loss-of-Lock Reset
The FMPLL provides the ability to assert reset when a loss of lock condition occurs by programming the
FMPLL_SYNCR[LOLRE] bit. Reset is asserted if LOLRE is set and loss of lock occurs. Because the
FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS] bits are reinitialized after reset, the system reset
status register (SIU_RSR) must be read to determine that a loss of lock condition occurred.
To exit reset, the reference must be present and the FMPLL must acquire lock. In bypass mode, the FMPLL
cannot lock. Therefore a loss of lock condition cannot occur, and LOLRE has no effect.
11.4.2.5.2 FMPLL Loss-of-Lock Interrupt Request
The FMPLL provides the ability to request an interrupt when a loss of lock condition occurs by
programming the FMPLL_SYNCR[LOLIRQ] bit. An interrupt is requested by the FMPLL if LOLIRQ is
set and loss of lock occurs.
In bypass mode, the FMPLL cannot lock. Therefore a loss of lock condition cannot occur, and the LOLIRQ
bit has no effect.