Associated Research HypotULTRA 7800, Руководство по эксплуатации и обслуживанию

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An Event register report defines conditions or messages at each bit. The bits are
latched and remain at an active state until the register is either Read or Cleared.
Reading the Event register automatically clears the register and sets all bits to inactive
state or 0. When querying an Event register the information is returned as a decimal
number representing the binary-weighted sum of all bits within the register.
The Enable registers bits represent the selection of bits that will be logically OR’d
together to form the summary bit in the Status Byte. The *CLS command will not clear
the Enable registers and if you wish to clear the register you must set it to a value of 0.
Like the Event register, the enable register is represented as a decimal number that
equals the binary-weighted sum of all bits.
The Enable register will clear to value a of 0 at power up unless the *PSC 0 command
had been executed before power-off. The *PSC command tells the device whether or
not it should clear the Enable registers at power-on. Using this command will allow
SQRs to function immediately after power-on.
EVENT REGISTER STATUS BYTE REGISTER
Bit Binary
weight
Event Register Enable
Register Summary Register Enable
Register
0 1 Operation Complete ALL PASS
1 2 not used FAIL
2 4 Query Error ABORT
3 8 Device Error TEST IN PROCESS
4 16 Execution Error Message Available (MAV)
5 32 Command Error Event Summary Bit (ESB)
6 64 not used Request Service (RQS) or
Master Summary Status
(MSS)
not
used
7 128 Power On PROMPT
*ESR? *ESE *STB? | SPOLL *SRE
*ESE? *SRE?
GPIB Service Request
The service request capability is not available with the USB/RS-232 interface. The
SRQ line will be activated only after one or more of the service request functions have
been enabled using the Status Byte Enable register command *SRE.
The Status Byte bit assignments are as described in the previous section for status
reporting. When the instrument has requested service, the enabled bit or bits and the
RQS bit 6 will be active or 1. Bits 4, 5, and 7 are not used and will be set to false, or 0
for all Status Byte reads.