Zenith Z-100 Series, Technical Manual

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Page 2.79
CIRCUIT DESCRIPTION
Interrupt on Terminal Count. The output goes to logic 1
when the counter reaches 0 (terminal count).
Programmable One-Shot. Not used since the gate lines are
tied to logic 1.
Rate Generator. This is a divide-by-n counter. The output
goes low for one clock period, returns high, and counts down
the number stored in the counter. When the counter reaches
0, the output pulses low again and the count starts over.
Square Wave Generator. The output remains high for one-
half the count in the down-counter, and then goes low for
the remaining count.
Software Triggered Strobe. After the mode is set, the output
is high. When the count is loaded, the counter begins count-
ing. On terminal count, the output goes low for one clock
penod.
Hardware Triggered Strobe. Not used because the gate
lines are tied to logic 1.
(See the 8235-5 data sheet in Appendix C for detailed hard-
ware and software information.)
The CPU selects the timer whenever it reads or writes port
OE4 through OE7. These ports select counters 0 through 2
and the control word register, respectively. Line 8253CS, from
the I/O port decoder, chip-selects U160 pin 21, while BAO
and BA1 select the internal counter or register.
The 8253CS line also enables the two OR gates connected
to pins 22 and 23 of U160. If the CPU is reading the data
in U160, it asserts the DBIN line at U113 pin 12. If it is writing
to U160, it asserts WR at U113 pin 10.