Zenith Z-100 Series, Technical Manual

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Page 6.50
INTERCONNECT PIN AND SIGNAL DEFINITIONS
Refer to the Schematic and pages 6.13-6.15 for pin and signal
numbers.
Address bits.
AO-A7
ALE
CLK
BDSEL
Address latch enable. Data and address
lines from the CPU have valid information.
The H/Z-207 board is selected (enabled).
Clock signal.
Chip select. When asserted, the 1797 chip
is enabled. CS
DIR
DRQ
DDEN
DO-D7
DIO-DI7
DOO-DO7
Data bits on the H/Z-207 board's internal
data bus.
Double-density enable.
Data-in bits on the S-100 bus ("in" with
respect to the CPU, not the controller).
Direction of drive head. When high, the
drive head is stepping in. When low, the
drive head is stepping out.
Data-out bits on the S-100 bus ("out" with
respect to the CPU, not the Controller).
Data r e q uest. T h e l 7 9 7 d a t a r e g i s ter
needs data for write operations or the re-
gister has data for read operations.
Drive select A. In combination with DSB,
addresses the drives.
DSA
DSB Drive select B. In combination with DSA,
addresses the drives.
Write data bit early to disk drive (used for
precompensation). EARLY