Zenith Z-100 Series, Technical Manual

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page 4.53
CIRCUIT DESCRIPTION
Converting RAM Data to Video
There are two sets of data lines at the video memory. One
is an 8-bit bus, BDO-BD7, used by the CPU to write to RAM;
and three 8-bit output buses, one for each color.
The output buses go to the CPU through U339, U310, and
U316. Only one of these ICs will be selected to place the
data on BDIO-BDI7. This, in turn couples through U223 to
the CPU. This will be covered in more detail later.
The three output buses also couple to the video processing
circuits through U332, U302, and U311. Here's how the data
is processed.
When the CRT-C has control of RAM (which is most of the
time, since it has priority), the VRAM is in the read mode.
This is due to a logic zero on VIDRAMSEL (U377 pin 4) and
CLRSCRN (U366 pin 3). When the addressed data settles,
VIDSTRB from U376 pin 17 asserts to latch and RGB data
into U332, U302, and U311. (Note: If this is a minimum system
— green only — U332 and U311 outputs will remain a steady
state.)
Next, the load shift register line from U320 pin 6 goes low
to latch the RGB data into the parallel-to-serial converters,
U325, U301, and U303. This line pulses at the character clock
rate.
The dot clock at pin 6 of these ICs then shifts the data out
through pin 13. This takes place at eight times the character
clock rate, or 14.112 MHz, which is the rate of the dot clock.
While the video information is being shifted out, VIDSTRB
is loading the next byte into D latches. When the last dot
is shifted out of the parallel-in/serial-out converter, the bytes
in the D latches are loaded in and the cycle repeats.
T he three serial dot lines connect to R IN , G IN, and BI N o f
U337, the VIDATTR PAL. Other inputs to U337 include the
FLASH line and three enable lines at pins 1, 2, and 3.