Zenith Z-100 Series, Technical Manual

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Page 6.26
DETAILED CIRCUIT DESCRIPTION
Read Status Latch (U31)
Assume that a status signal needs to be read. There are two
sources of status information for the S-100 bus, the status
port and the status register in the 1797. To read the status
port, the following happens. The Card is selected by the CPU,
which does this by placing the address of the Card on address
lines AO-A7. Address lines A3-A7 are checked by the address
comparator U29 for the proper address. (The proper address
is defined by the user by setting DIP switch DS1.) If the ad-
dress is proper, U29's EOUT signal is activated on U29's pin
19.
The EOUT signal is gated in U28, NOR gate D, with signal
I/O. If signal I/O is low, indicating that the slNP (input) signal
or sOUT (status output) signal from the CPU is also present,
the simultaneous assertion of EOUT and I/O signals are
passed to U20B, a flip-flop whose Q and Q outputs are as-
serted when the A d dress Latch Enable (ALE) signal clocks
its pins 3 and 11.
The Q output of U20B is ANDed in U27, NAND gate C, with
pDBIN, the S-100 data input control signal at pin 78 of the
bus interface. The output at pin 8 of U27 becomes low, indicat-
ing that the Floppy Disk Controller Card is being read by the
CPU, and activates the enable 1 line of the status latch, U31.
The status latch still can not be read until the status port select
line (STPS) is asserted at pin 15 of U31. The enable line
is activated by U17, the I/O address decoder.
The I/O address decoder activates STPS by decoding address
line AO, A1, and A2. If AO and A1 are low and A2 is high,
and if BDSEL or card select is active, the U31's Y1 line is
made active. U31 then outputs its status word to the Card's
internal data bus, w here it is buffered by U3 6 to th e S - 100
bus.