Zenith Z-100 Series, Technical Manual

Page: 368 / 493

Page 6.29
DETAILED CIRCUIT DESCRIPTION
The 1797 fills its data register from the data shift register,
which fills serially from the processed RAWDATA data stream.
(RAWREAD data processing is discussed in "Data Separation
and Precompensation" on Page 6.30.)
RDY Delay
U19 is a quad flip flop that acts as a delay line for the DRQ
signal from the 1797 to the RDY line to the CPU at pin 72
of the S-100 bus interface. The input at D1, pin 4 of U19
is output at Q1 after one clock cycle. Q1 is tied to D2 and
is output to Q2 after another clock cycle. Q2 is also tied to
U25, gate A, and D3. From gate A, the D2 signal presets
flip flop U26, part A. Flip flop U26 qualifies the FDSEL signal
to enable read/write operations in anticipation of the RDY line
being made active.
From D3 of U19, the DRQ signal is output to Q3, which is
connected to D4 and to jumper J1, post G. Post G is con-
nected to post F in 3-MHz operations, which do not need
additional delay of the DRQ signal. Instead, the output of Q4,
which contains the DRQ signal delayed by three to four clock
cycles, is connected to jumper J1, post E. For most 6-MHz
operation, J1 is connected between post E and post F. For
the Z-100 series of Computers, the Computer's internal timing
requires that the 6-MHz jumper be used.
Data Shaping
Data pulses to the drive are reshaped by U16, a one-shot
multivibrator, to 400 ns. Raw data from the drive is reshaped
to 250 ns.