Zenith Z-100 Series, Technical Manual

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Page 2.89
CIRCUIT DESCRIPTION
pin 40 causes IRQA at pin 38 of U114 to go low if unmasked
by software. IRQA is then inverted by pin 13 of U134 to cause
a display interrupt at the CPU.
When the CPU acknowledges the interrupt, it must assert the
6821CS line (from the I/O decoder port) at U175 pin 4. Line
6821CS also chip-selects U114 at pin 23, while BAO/BA1 ad-
dresses the PIA control register to see if the light pen circuits
generated the interrupt. The OUT line at pin 21 and the DBIN
l ine at U 17 5 pi n 1 0 g o t o l o g i c 1 t o t r a n sfer the PI A d a t a
to the CPU.
If the interrupt was caused by light pen activity, the CPU pro-
cesses it according to its program. Before finishing, the CPU
clears pin 5 of U131 by pulsing a logic 0 to pin 1 of U131.
U134B, the light pen switch inverter, allows the CPU to moni-
t or the status of a S P S T s w i tch c o nnected to L T P NSW a t
J4. It does this by continually polling PA6 at U114 pin 8. This
allows the Computer operator to do s uch t hings as m ove a
dot around the CR T f ac e w ith the l ight pen. As b e fore, the
Computer must be programmed to use this feature.
Video Interrupt Port
The video interrupt port consists of U116G, U131, and U114.
The signal at pi n 1 6 o f U 1 16 , V I D INT, is th e v e rtical sync
pulse, VSYNC1D, buffered through pin 9 of U366 on the video
b oard. The C P U t i me s i t self from t his p u lse s o t ha t i t c a n
update the display during vertical retrace, thus preventing in-
terference on the display. See the "Video Board" circuit de-
scription for more details.
When a vertical sync pulse occurs, the positive-going edge
from pin 5 of U116 latches a logic 1 into pin 9 of U131. This
couples to U114 pin 39, and causes the PIA to generate a
display interrupt at U114 pin 38.
When the CP U r e sponds, it checks the PIA control register
to determine which line c a used th e i n terrupt. Once it f i nds
that VIDINT caused it, the CPU clears U131 by pulsing U114
pin 7 low, and then updates the display circuits as necessary.