Zenith Z-100 Series, Technical Manual

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Page 2.33
CIRCUIT DESCRIPTION
Processor Swap Port
General
The processor swap port controls which CPU is to be active,
handles interrupt routing, and ensures proper timing of the
clock circuits during the swap. To access the swap port, the
CPU writes a control byte to port OFEH. Only three bits of
the byte are used: ADO controls the automatic wrap and/or
mask mode, AD1 controls the swap interrupt line, and AD7
performs the processor swap.
At power up, the reset circuits clear U171 pin 9 to logic 0.
This pin, 8SEL, connects to U186, a 12H6 PAL, through pin
5. This IC responds by placing a logic 0 on U187 pin 12 and
a logic 1 on U187 pin 2. On the first positive transition of
854, the 85HOLD line goes low, enabling the 8085 CPU. On
the first positive transition of 884, the 88HOLD line goes high,
disabling the 8088 CPU.
The 8085, while executing the code in the monitor ROM, soon
transfers control to the 8088. It does this by setting bit 7 of
the processor swap port control byte to logic 1 by writing to
that port.
The CPU address port OFEH asserts SWAPCS (from the I/O
decoder) at U206 pin 5. It then sets AD7 to logic 1 at U171
pin 12. Finally, it asserts the write line at U206 pin 6. As a
result, U171 pin 11 goes high and latches U171 pin 9 to logic
1. The 8SEL line is now asserted. The values at U172 pin
12 and U172 pin 2 are also latched to their respective outputs.
The 8SEL line, now logic 1, causes U186 pin 13 to change
to logic 1, pin 18 to change to logic 0, and pin 16 to change
to logic 1. This last line, 88SEL, couples to U215 to form
the S-100 bus line (pin 21), NDEF (8088). This line is a "not-to-
be-defined" line that can be used for any function. In the Com-
puter, this line asserts when the 8088 is active.