Zenith Z-100 Series, Technical Manual

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Page 6.51
INTERCONNECT PIN AND SIGNAL DEFINITIONS
HLD
Head load.
Head load timing. The drive head is not
engaged when this signal is low.
HLT
MR
LATE
INDEX
INTRQ
The index hole on the diskette has been
detected.
Interrupt request. H/Z-207 board has input
for the CPU.
Write data bit late for drive precompensa-
tion.
Master reset pin on the 1797 Controller
chip that sets all registers in the chip to
a known state.
Data request on data-in bus.
pDBIN
pSTVAL"
pSYNC
PU
PD
pWR
PRECOMP
RAW READ
Satus valid.
New bus cycle may begin.
Pump down. Decreases the frequency of
the raw read data tracking clock.
Enables precompensation when low.
Pump up. Increases frequency of the raw
read data tracking clock.
Valid data is on data-out bus (write bus).
Unprocessed data from the drive.
Clock that separates data from drive data
and clock stream.
RCLK