Zenith Z-100 Series, Technical Manual

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Page 2.60
CIRCUIT DESCRIPTION
Number of inputs
that are high. Outputs
E ven O d d
H L
0, 2 , 4, 6, 8
1, 3 , 5 , 7, 9
So if there is an odd number of high bits in the data byte,
the logic 1 on pin 4 of U153 makes the number even. U153
pin 5 responds by going high. If there is an even number
of data bits in the data byte, pin 5 of U153 stays low, so
the total bit count remains even. U153 pin 5 couples the 1
or 0 through the normally-enabled gate at U151 pin 4 to the
data input pins of the parity RAMs.
L H
The ZEROPAR line at U151 pin 5 is normally high. This can
be brought low to force all addressed parity RAM locations
to 0, regardless of the byte status. It is brought low by clearing
data bit D4 to logic 0 and outputting the bit to port OFCH,
the memory control latch. (ZEROPAR is used as a quick test
to see if the error-detection circuits work.)
The odd-parity output goes to U152, pin 11. During a memory
write, pin 11 is low, preventing an erroneous error signal from
being generated. For the same reason, U151 pin 9 remains
low for a memory refresh.
During a memory read, data output from the addressed RAMs
are present at the inputs of U153. The corresponding parity
bit, from U101, U117, or U137, is placed on U153 pin 4. If
the bit pattern that was previously written into data RAM and
parity RAM has not changed, the total number of high bits
is always even. So U153 pin 6 remains low, which is the no-
error condition.
If, however, the bit count is an odd number — due to a chip
failure or soft error, for example — then U153 pin 6 goes
high. When TAP2 goes low, pin 9 of U152 is latched to logic