Zenith Z-100 Series, Technical Manual

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Page 2.47
CIRCUIT DESCRIPTION
pWR*, pin 77 (valid write data). This is a generalized write
strobe that writes data from the data bus into memory or an
output port. It is timed with pSYNC and pSTVAL* to ensure
that the data is valid on the DO bus before a write takes place.
The CPU write command is inverted through U220 pin 12
and applied to U235 pin 13, a three-input NAND gate. The
pSTVAL* line connects to pin 1 of this gate and prevents
a write from taking place until the address lines are stable.
The inverted pSYNC, at U235 pin 2, ensures that a pulse
does not occur on the pWR* line before data is valid on the
DO bus.
CDSB* and MWRT, pins 19 and 68 (control disable and
memory write). These lines are not control output lines but
are associated with them.
Asserting the CDSB* line 3-states U180 to disconnect the
bus control lines. This situation can happen if another CPU
board that is plugged into the S-100 bus takes control of the
bus. If so, that board must supply the output control signals.
While pWR* is a generalized write strobe for both memory
and output ports, MWRT is a write strobe for memory write
cycles only. In the Computer, it is used in the memory circuits
and on the video board. This signal is derived by NORing
pWR* and sOUT (from the status circuits) at U216C.