Zenith Z-100 Series, Technical Manual

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Page 2.71
CIRCUIT DESCRIPTION
If the 8085 is active, the following sequence occurs:
1. Th e C PU asserts the INTA line at pin 26 (of 8259A).
2. U2 0 8 p l aces the 8080/8085 CALL instruction (OCDH)
onto the data bus at pins 4 through 11.
3. T he 8 0 85 decodes this call instruction and determines
that it requires two more bytes. It then sends two more
INTA signals to U208.
4. Wh e n U208 receives the second INTA, it sends the low
byte of the vector address to the CPU. When it receives
the third INTA, it sends the high byte of the vector ad-
dress to the CPU. (The vector addresses must be pro-
grammed into the 8259A during the initialization pro-
cess.)
5. Aft e r saving its current location in stack, the CPU jumps
to the address supplied by the 8259A to process the
interrupt. When it finishes, the CPU returns to the loca-
tion saved in stack and continues the program it was
processing before interruption.
When the 8088 CPU is active, the 8259A responds somewhat
differently to an interrupt acknowledge:
1. T h e C P U asserts the INTA line at pin 26; the 8259A
does not respond at this time.
2. T h e C PU again asserts INTA on the next machine cycle.
3. T he 8 2 59A places a byte on DO-D7 that respresents
the interrupt type. The interrupt type is an 8-bit number
that depends on which interrupt line caused the inter-
rupt.