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Zenith Z-100 Series, Technical Manual

The Zenith Data Systems Z-100 Series is a cutting-edge computer system with powerful capabilities. For detailed information on setting up your device, be sure to download the free Installation Manual from our website. Get your hands on this essential manual and unleash the full potential of your Z-100 Series computer.

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Summary of Contents for Z-100 Series

Page 1: ...595 2918 04 FLYSHEET 597 2792 04 TAB SET VOL I 597 3437 TAB SET VOL II 5974438 SCHEMATIC ENVELOPES 597 29184 2 MAIN BOARD SCHEMATIC 585 018 02 VIDEO LOGIC SCHEMATIC 585 0019 01 VIDEO DEFLECTION SCHEM...

Page 2: ...This Document was scanned and contributed by...

Page 3: ...ta sheets and the iAPX 88 Book Place this last item in this binder as it includes the 8088 architecture and instruction set ROM Source listings These volumes are printouts of the source code used in t...

Page 4: ...ption User Options and Programming Theory of Operation Troubleshooting Keyboard Scan Matrix Encoder Output Codes Keyboard Key Layout Chapter 4 Description User Options and Jumpers Theory of Operation...

Page 5: ...ooting Recalibration Parts List Circuit Board X Ray View Chapter 6 Description User Options Programming Data Theory of Operation Circuit Description Troubleshooting Calibration Parts List Semiconducto...

Page 6: ...42 10 52 10 59 10 60 Chapter 10 Description General Information Devices Permitting User Programming Port Addresses Z DOS Initialization Sequence ASCII Chart Escape Codes Definitions Key Code Chart Ke...

Page 7: ......

Page 8: ...llowing use of software for either up to 3 4 megabyte of user addressable memory RAM an S 100 IEEE 696 standard bus with five slots for expan sion two RS 232 serial input output ports on e parallel ou...

Page 9: ...provided through the use of an 8 bit pro cessor an Intel 8085 for 8080 code and a 16 bit processor an Intel 8088 for 8086 and 8088 code The 8 bit processor allows you to use many of the large number...

Page 10: ...IGHT PA RAL L EL SE RIA L PEN IN TERFA C E IN T E RFACE CARD FLOPPY DISK CONTROLLER EXTERNAL 8 INCH DRIVES INTERFACE POWER SUPPLY WINCHESTER CONTROLLER INTERNAL 5 25 INCH DRIVES CARD 8085 5 8088 CPU 3...

Page 11: ...ches and jumpers on the main board control autobooting vertical scan frequency interfacing for the serial ports and PROM size 8 16 or32K x 8 Temporary master processors on cards plugged into the back...

Page 12: ...is directly accessible from the S 100 bus and may controlled by either temporary or master processors The CRTC video control bits and video RAM are all accessi ble from the S 100 bus and are compatib...

Page 13: ...Winchester drives Note that Zenith Data Systems supports operating system software for only one Winchester drive at this time for single user installations Other Options Other optional S 100 cards are...

Page 14: ...l cards can be added to accommodate ad ditional memory additional input output ports and the Zenith Local Area Network Z LAN When you are disassembling your system keep in mind there various options a...

Page 15: ...tely 1 4 inch as shown Carefully lift off the cabinet top and set it to one side On the All in One models you will have to use a flat bladed screwdriver as illustrated in the pictorial TOP o CA B I NE...

Page 16: ...om the front of the computer you will have to remove the cables going from the Winchester card to the drive Likewise if you are removing the Winchester controller card for installation of the jumper f...

Page 17: ...hrough holes in the cabinet slides Lift the display and disk drive as sembly up and forward a short distance LOOSEN g 1 P v LOOSEN SCREW SCREW LOOSEN SCREW LOOSEN SCREW REMOVE SCREW lol I I lol I I I...

Page 18: ...he flat cable from the floppy disk controller card the power supply cable s at the drive s and the video signal power cable on the video deflection board DR IVE V IDEO SUBASSEMBLY I VIDEO S I GNAL POW...

Page 19: ...r controller card the power supply cables from the drives and the video signal power cable on the video deflection board iL S S W C W S S S S S C 5 I GNA L POWER Q a d i 1 CA BLE FLOPPY I DISK Qi D R...

Page 20: ...emove the four screws a B Lift the front panel and is computer an o e disk drive assembly out o rews at A and two locking pins at of the d t the front a short distance LOCK I NG PIN u SCREW i rIffr l...

Page 21: ...ystems only remove e the flat cable from the floppy disk drives and the power supply cable s at the drive s DR IVE Set the assembly aside s U BAs s EMBLv FLAT CABLE POWER ABLE 8l l l f i z i i i y y i...

Page 22: ...the Winchester controller card the flat cable 134 1284 from the floppy disk con troller card and the power supply cables at the drives Set the assembly aside DRIVE DATA SEPARATOR BOARD CA BLE POIiIiE...

Page 23: ...s at A from near the top of the keyboard Low Profile models only remove the two locking pins at B from near the rear of the computer Lift off the keyboard shell Set the shell to one side KEYSOA RO SHE...

Page 24: ...GENERAL INFORMATION Disassembly Refer to Pictorial 1 11 Move the keyboard forward and unplug the two cables from the main board Set the keyboard to one side NIAIN KEYSOARD Pictorial 1 11 Removing the...

Page 25: ...upply that hold it to the base Lift the power supply out of the computer and set it to one side WARNING There are no user serviceable parts inside your power supply Never open it up or break the seal...

Page 26: ...ove the two screws at C from the rear panel as illus trated Remove the four screws at D from the base as illustrated Remove and set the card cage toone si de Vm ym D POWER SUPPLY pm S 100 CARD CAGE 9...

Page 27: ...o Pictorial 1 13 Remove the three screws holding the board to the three hex mounting spacers Unplug the two cables from the main board Remove the circuit board and set it to one side c C 0 0 3 0 0 3 0...

Page 28: ...spacers at A from the main board Remove the nine screws at B from the main board Remove the main board and set it to one side This completes the disassembly of the modules of your com puter The next...

Page 29: ...rives All in One Models Refer to Pictorial 1 15 Note that this pictorial illustrates a two drive half height module the following instructions apply equally to all configurations of the All in One com...

Page 30: ...HEAD I SCREW I I I II I II I II I II I ll I II I I l I 1l I I I I I I I I i I I I i I il I I ii I 4 II I I j I I III I I l l I I II I ill j Ii GROUND STRAP I il I I I I I I i I li I I I ilD I r I I I...

Page 31: ...zed floppy disk system Your system whether it is a half height or floppy disk only version will be similar Remove the three screws at A and remove the front panel and panel from the assembly Co x x DR...

Page 32: ...s at A and remove the data separator board set it to one side Full sized floppy disk drives only remove the four screws at B and remove the Winchester disk drive Full sized floppy disk drives only rem...

Page 33: ...ppy disk drives only remove the four screws at B and remove the floppy disk drive Half height floppy disk drives only remove the four screws at C and remove the Winchester disk drive I go DR VE CHASSI...

Page 34: ...m y e i notbecontaminatedbydust lint paper orot ero j Refer to Pictorial 1 19 Winchester versions only remove the four screws at B and remove the data separator board Winchester versions only remove t...

Page 35: ...ons only remove the two flat head screws that hold each side bracket to the drive Note the placement of the mounting screws in the side bracket the position and holes used will vary according to the d...

Page 36: ...ORMATION Disassembly DISK DRIVE I L i DRIVE SHELF i li Q ll L EFT SI D E BRACKET 6 32 X3 8 HEX HEAD SCREW DR IV E SHIELD el p R IGHT SI D E BRACKET 6 32 x3 8 FLAT HEAD SCREW Pictorial 1 20 Removing th...

Page 37: ......

Page 38: ...ers Programming Information Theory of Operation Circuit Description Replacement Parts List 219 2 23 2 3 2 6 2 92 Semiconductor Identification Circuit Board X Ray Views 295 2 136 Interconnect Pin Defin...

Page 39: ...ure 8 bit processor The main board also contains up to 32k bytes of ROM and up to 192k bytes of RAM with parity There are two serial ports a parallel printer port a light pen port a keyboard and a tim...

Page 40: ...2 2 2 2 OIjljc 2 J104 4 J105 ll J106 J J 2 P ON SOME BOARDS 2222 222 J109g rcnJ111 s Pictorial 2 1 Main Circuit Board...

Page 41: ...r your system and pre ferences Switch S101 Section Descri tion Default boot device 1 Auto boot 0 Manual boot not used 0 60 Hz 1 50 Hz for video vertical scan frequency Sections 0 1 and 2 should be set...

Page 42: ...errupt The position shown causes an interrupt on the negative going edge It is properly jumpered for operation with a light pen that causes a negative pulse during a hit J104 No jumper is needed at th...

Page 43: ...ion to its normal interrupts J109 This jumper connects serial port A DCD input to either ground or RTS from the connector It is normally set in the mode shown that connects DCD to RTS J110 Same as J10...

Page 44: ...resses are for devices located on the main board A more complete list can be found in Pro gramming Data Device Name Port Address HEX DIP Switch Processor Swap High Address Latch Memory Control Latch F...

Page 45: ...l A 2661 Serial A 8253 Timer 8253 Timer 8253 Timer 8253 Timer Ej E6 E5 E4 68A21 Parallel 68A21 Parallel 68A21 Parallel 68A21 Parallel E3 E2 E1 EO Port Bit Definitions The definitions given below are f...

Page 46: ...FF D7 D6 D5 D4 D3 D2 D 1 DO Default Boot Device 1 Auto boot 0 Manual boot 1 50 Hz Switch S101 Section Deecri ticn Default boot device 1 Auto boot 0 Manual boot not used not used not used 0 60 Hz 1 50...

Page 47: ...port is the masking of interrupts If interrupts are not masked the currently selected processor is signaled when an interrupt is requested If the MASK mode is selected no interrupts will get through t...

Page 48: ...24 bit addresses The 8088 naturally has 20 bits of addressing The upper four bits placed on the bus are controlled by HIGHADDR The hardware automatically selects bits A16 A19 coming from the 8088 when...

Page 49: ...C RAM Configurations ROM Configurations Zero Parity Kill Parity The following chart shows which port bits control the various RAMconfigurations BITS DEF INITION 1 0 00 Option 0 10 Option 2 01 Option1...

Page 50: ...e ROM Parity consists of a parity bit for each byte in RAM This adds one two or three 64K bit chips depending on how much RAM is installed 64K 128K or 192K and the associated support circuitry RAM par...

Page 51: ...ided which can be read to deter mine which of the channels caused the interrupt TMRSTAT Outputs of these latches are OR ed together to produce the interrupt input to the 8259 To find out which timer c...

Page 52: ...l counter 1 000 Mode0 2 X 10 Mode 2 3 100 Mode4 001 Mode1 X11 Mode3 101 Mode5 4 00 Counter latch 01 5 10 Read load most 11 Read load least significant byte only Read load least significant byte then m...

Page 53: ...The slave 8259A handles only the vector interrupts you configure your hardware to generate Timer Port Address Block Diagram Master 8259A IO S 100 error signal parity error from main l1 Processor swap...

Page 54: ...E2 CRB2 2 IRQB1 IRQB2 CA1 LTPNSTB light Pen Strobe CA2 QVIDINT Latched Vertical Sync CB1 ACK Printer Acknowledge Signal CB2 BUSY Printer Busy Signal CB2 Control CRB2 Peripheral Register A Data Direct...

Page 55: ...is read by Port B bit 1 The printer may be initialized by activating the INIT line by Port A bit 3 The CPU will not respond to a signal from the light pen circuits It requires a user supplied program...

Page 56: ...hed by two 4 bit address latches The total address width then becomes 24 bits The 8088 on the other hand is built to generate 20 bit addresses This capability has been extended by 4 bits which are sim...

Page 57: ...Hz 8085 NMI 8085 SELECT 16 8 IT C PU DMA REQ 8088 5MHz INTR DATA ADDRESS AO 15 CPU SELECTION LOG IC 4 BIT LATCH 1 2 U624 DMA REQUEST 4 8 IT LATCH I 2 U624 MASK C KT INT REQUEST MID ADD BITS 4 A 16 A 1...

Page 58: ...recomputes the parity and checks it against the value stored in parity RAM every time a word is read from data RAM If a discrepancy is found a parity error interrupt is sent to the 8259 interrupt con...

Page 59: ...Circuitry This circuitry consists of two 8259A interrupt processors one a master and the other a slave See Pictorial 2 4 The slave 8259A services vector interrupts from the S 100 bus if the hardware...

Page 60: ...RESET KEY STROBE EXT KEYBOARD KEYBOARD DATA Pictorial 2 5 Keyboard Block Diagram KEY CLICK I O Circuitry The I O circuitry consists of a 6821 parallel printer port two 2661 2 serial ports and a TTL co...

Page 61: ...escriptions in this Nlanual active low signals may be designated as such othe traditional bar over the signal name e g SlGNAL Pin Out Description A8 A15 pins 21 28 3 state address These multiplexed li...

Page 62: ...ALT and RESET WR pin 31 3 state write control This output line goes to logic 0 to indicate that the data bus is ready to transfer data from the CPU to memory or I O Data is set up on the trailing edge...

Page 63: ...est priority interrupt and cannot be disabled RESETIN pin 36 reset input Bringing this input line low resets the Computer It sets the program counter to 0 disables interrupts and resets the HLDA flip...

Page 64: ...uction Though there are seven possible types of machine cycles see the data sheets these waveforms are typical During the M1 cycle the Computer fetches the op code in this example the OUT instruction...

Page 65: ...icated by the logic states on status lines S1 and SO At time T2 to T3 RD goes low to read the memory location pointed to by the address latches This location contains the address of the I O port to be...

Page 66: ...us lines in the 8088 are identical to the 8085 at U210 Some of the features of the 8088 are A 20 bit address bus allowing the 8088 to directly address up to 1 megabyte of memory A 16 bit input output...

Page 67: ...4 N WAIT I TCY T I l T2 l T3 i TwAO l T4 TI T2 i 73 l TwAIT l T4 CLK GOES INACTIVE INTHE STATE JUST PRIOR TO T4 ALE so A g AIG A g AIS ST S3 AODR STATUS AOOR AIS AB AIS AB AOOP DATA BUS R E SERVEO O 0...

Page 68: ...is brought to a high impedance state during HLDA ALE pin 25 address latch enable This line pulses high when the CPU places the address information on the address data bus In the Computer this line clo...

Page 69: ...ts see the interrupt circuit description for more details HLDA pin 30 hold acknowledge This pin goes high to indicate that the CPU has acknowledged a hold request at pin 31 HOLD pin 31 hold request Th...

Page 70: ...he 8088 READY pin 22 ready This is an acknowledgement signal from the addressed memory or I O port that it is ready to transfer data When this line is low the CPU goes into a wait state until the addr...

Page 71: ...ition of 884 the 88HOLD line goes high disabling the 8088 CPU The 8085 while executing the code in the monitor ROM soon transfers control to the 8088 It does this by setting bit 7 of the processor swa...

Page 72: ...ke control of the Computer Swap Timing The 88SEL line also goes to U188 pin 4 a quad D type latch that suppresses any glitches on the system clock line when the Computer switches from one CPU to the o...

Page 73: ...00 pin 2 and U200 pin 14 Assuming that the 8085 is the active processor then U200 pin 1 is low and 85C couples through the inverter to form S4 It also couples through U2258 to clock U188 At time T1 th...

Page 74: ...the gate at U225A to pass the system clock which is now the 8088 signal As mentioned earlier the other function that 88SEL and U188 performs is to ensure that the CPU being disabled is com pletely dis...

Page 75: ...it MSK is set or cleared by setting or clearing bit 0 of the processor swap port If cleared and the 8085 is active the 8085 gets all inter rupt requests If set and the 8085 is active the interrupt re...

Page 76: ...U225 pin 10 all interrupt requests are routed to the 8088 processor Swap Interrupt Whenever one of the CPUs is placed into the HOLD state it does not lose the contents of its registers This way when t...

Page 77: ...ets the video board through U215D and P106 pin 64 U201A buffers the reset signal to provide the S 100 SLAVE CLR signal Because U207 pin 8 controls U201A through its gate line pin 1 SLAVE CLR is logic...

Page 78: ...U239 S101 and U156A make up the DIP switch select cir cuits The position of these switches determine the operating mode of the Computer The Computer reads the status of S101 during power up by addres...

Page 79: ...kept disabled by connecting U227 pin 18 to logic 1 However if a true 16 bit CPU board is plugged into the S 100 bus the Computer can be programmed to give control to this CPU and this CPU can perform...

Page 80: ...d data from the addressed input port sMEMR pin 47 memory read This line asserts to indicate that the CPU is going to read data from the addressed memory location sHLTA pin 48 halt acknowledge This lin...

Page 81: ...uses U227 to correctly decode the bit pattern on pins 10 11 and 12 as an 8085 status code U226 decodes this status which is subsequently latched into U227 when ALE goes low The following chart shows t...

Page 82: ...memory or I O access the wait line asserts according to the chart above The asserted wait line is inverted by U206A to clear pin 9 of U205 This logic 0 couples directly to the 8085 READY input and ind...

Page 83: ...Pictorial 2 8 as each output line is discussed pSYNC pin 76 synchronization This line goes high to indi cate the start of a new bus cycle Basically it is the ALE signal of the currently active CPU ret...

Page 84: ...hich occurs after the negative going edge ofpSTVAL pHLDA pin 26 hold acknowledge This is the hold ac knowledge signal it goes high when both the 8088 and the 8085 are in a hold state Such a situation...

Page 85: ...es that a pulse does not occur on the pWR line before data is valid on the DO bus CDSB and MWRT pins 19 and 68 control disable and memory write These lines are not control output lines but are associa...

Page 86: ...6 has had time to stabilize U221 11 goes high clocking the data bus signals into U176 on the positive going edge The bit pattern that was on the data bus is now latched onto the Q outputs of U176 sett...

Page 87: ...A7 One of the three RAS lines 0 2 asserts to latch this address into RAM The upper eight bits of the address are placed onto MAO MA7 After waiting a short time for the lines to settle the CAS lines as...

Page 88: ...MAO MA7 which are the upper eight bits of the address Forty nanoseconds after TAP1 asserts TAP2 at pin 5 of U110 goes high This clocks MAO MA7 into the CAS latches Another line going to the multiplex...

Page 89: ...ontiguous RAM from 0 t o 192K Under normal operation BA16 and BA17 select the banks as follows BA17 BA16 Condition 0 0 0 to 64K RENO asserted 0 1 64K 1 to 128K REN1 asserted 1 0 128K 1 to192K REN2asse...

Page 90: ...on U133 pin 1 tri stating this buffer During memory write PHANTOM prevents WE from asserting causing a dummy read cycle Refer to the timing diagram in Pictorial 2 10 as the basic timing cycle is disc...

Page 91: ...154 5 U170 6 STC TA P1 TA P2 R STC TA P1 TAP2 60 60 R 8 0 R OUT U144 8 80 ouTIui44 8 C LRNIR U151 12 RREQ BCYC CLRMR U151 12 RREQ BCYC CLRRR U168 3 REN 0 RAS 0 RAS 0 RA CLRRR U168 3 REN 0 RAS 0 S 2 CA...

Page 92: ...This line is normally low for CPU accesses to any memory locations below 256K If above 256K one of the extended address lines BA18 BA23 will be high which will raise DECODEN This in turn forces all o...

Page 93: ...plete Also the refresh circuits provide timing for RAS CAS BCYC and other memory functions for both refresh and CPU operation as explained below U147 a 16 us oscillator generates the refresh clock The...

Page 94: ...P1 by 40 ns Since BCYC is low U110 in the memory mapping circuits recognizes that this is a refresh cycle When TAP1 goes high all three RAS lines assert This refreshes the entire row pointed to by U12...

Page 95: ...RASO on pin 19 of U110 to assert The lower eight bits on MAO MA7 are loaded into the RAM s row address latches STC also drives U144 a 200 ns delay line with 40 ns taps TAP1 asserts 40 ns after STC an...

Page 96: ...into MAO MA7 When TAP1 goes high all three RAS lines assert to refresh memory as described previously The RAS lines return high at the end of TAP1 time and U173 asserts the clear refresh request line...

Page 97: ...onsist of U153 U101 U117 U137 and U152 These circuits maintain the parity status for each byte in the 192K of RAM If a memory location s parity is in error then the parity circuits send an error signa...

Page 98: ...to logic 0 and outputting the bit to port OFCH the memory control latch ZEROPAR is used as a quick test to see if the error detection circuits work The odd parity output goes to U152 pin 11 During a...

Page 99: ...n Map selection takes place at pins 1 and 5 of U111 These two lines MAPSELO and MAPSEL1 also go to pins 7 and 8 of U173 but currently are not used by this IC Depending on the logic state of pins 1 and...

Page 100: ...6K area remainunchanged as does the top 64K bank This con figuration would permit using an extended BIOS when running CP M 2 2 8 bit operating system software Note that in all cases the memory only ap...

Page 101: ...as explained below After power up or a hard reset the memory control latch at U176 is cleared by the reset line at pin 1 This places lines PROMO and PROM1 of U161 pins 14 and 17 at logic 0 When both P...

Page 102: ...rol latch Data bit D2 directly affects PROMO and D3 affects PROM1 The PHANTOM Line The PROMSEL line from U161 also connects to U194 pin 5 an open collector buffer that connects to the PHANTOM line on...

Page 103: ...and sends them to their appropriate latches Under normal operation the CPU selection logic enables either the 8085 CPU or the 8088 CPU Although the address data lines of these processors are connecte...

Page 104: ...r eight bits PA8 PA15 go to U196 These latches are transparent as long as the ALE line is high that is the output logic levels are the same as the input logic levels At the end of T1 ALE goes low to l...

Page 105: ...ddress on U197 and U196 U198 pin 1 is the inverted version of DODSB from the S 100 bus This signal functions in the same manner as ADSB If the CPU is reading data either from memory or an input port i...

Page 106: ...placed on lines AD4 AD7 at U212 Lines ADO AD3 are blocked by U193 At the end of that cycle the CPUWR line goes high and latches AD4 AD7 onto the outputs of U212 At the beginning of the next machine cy...

Page 107: ...n Before the 8259A can be used the CPU must initialize it The CPU does this by outputting the programming information to ports OF2H and OF3H for the master and to OFOH and OF1H for the slave When it a...

Page 108: ...port B interrupt KEYINT or D SPYINT Interrupt from the keyboard vertical sync or light pen circuits PRINTINT Interrupt line from the parallel print er port Maskable Interrupt Sequence Whenever one or...

Page 109: ...vector addresses must be pro grammed into the 8259A during the initialization pro cess 5 Aft er saving its current location in stack the CPU jumps to the address supplied by the 8259A to process the...

Page 110: ...interrupt lines If one of these lines is asserted U209 pin 17 goes high to cause a level 3 interrupt at U208 pin 21 This in turn sends an interrupt request to the CPU through U158C When the CPU respon...

Page 111: ...MI and PWRFAIL both from the S 100 bus NMI is a general S 100 bus nonmaskable interrupt line It can be used by S 100 boards to signal the CPU of a catas trophic event such as imminent loss of power me...

Page 112: ...NMI occurs while the 8085 is active U189D sends it to the TRAP input at U210 pin 6 If the 8088 is active U189C sends the interrupt to U211 pin 17 If either an interrupt request or an NMI occur U156B a...

Page 113: ...mation and to write command words to the UPI CS pin 6 chip select line When the CPU addresses the keyboard circuits at ports OF4H and OF5H the I O port de coder asserts line KEYBDSEL This activates U2...

Page 114: ...key is also pressed If so the UPI jumps to a routine that translates the keypress at ROWO ROW7 to its appropriate shifted code if it has one TO pin 1 test line 0 When a key is pressed the UPI checks t...

Page 115: ...INT sending a keyboard interrupt to the CPU P27 pin 38 bell and keycllck This bidirectional I O line is programmed as an output It pulses to generate the bell and key click sounds U183 NORs this line...

Page 116: ...med The read write logic allows the CPU to communicate with the 8253 5 It communicates through the data bus buffer when CS and either RD or WR are asserted Address lines AO and A1 connect the data bus...

Page 117: ...is set the output is high When the count is loaded the counter begins count ing On terminal count the output goes low for one clock penod Hardware Triggered Strobe Not used because the gate lines are...

Page 118: ...t both status latches have previously been cleared When counter 2 counts down to 0 U160 pin 17 goes low for one clock period and then goes high again This positive going transition latches a logic 1 i...

Page 119: ...ideo board The combination of IO a n d STVAL SYNC form CSEN at U238 pin 9 This line provides a chip enable signal to serial ports A and B At the end of the read or write pulse from U224 pin 1 the logi...

Page 120: ...operation Asynchronous or synchronous operation 5 to 8 bit characters plus parity Odd even or no parity Baud rates f rom 45 5 baud to38 400 baud Full handshaking See the 2661 2 data sheet in Appendix...

Page 121: ...a to be transmitted on the inputs of U244 and asserts sWO at pins 1 and 19 of U244 The data is loaded into the transmit data holding register in side the EPCI The EPCI then asserts TxRDY at its pin 15...

Page 122: ...dy DTR To maintain RS 232 standards they are swapped with their com p ementary lines at the DCE connector Jumpers J109 and J111 allow connecting the DCE RTS line to either CTS or to DCD on the EPCI If...

Page 123: ...H Mod e registers read write OEFH Comm and registers read write The differences between this port and serial port A are minor To chip select this IC the CPU asserts EPCIBCS instead of EPCIACS the EPCI...

Page 124: ...O and BA1 pins 36 and 35 to select the correct internal register The enable line E CLK comes from the E clock logic circuits described previously and provides timing to U114 All other signals to the P...

Page 125: ...going or positive going signal allowing ACKNLG to assert on logic 1 or a logic 0 Some printers handshake when busy CB1 detects the voltage transition and asserts the printer inter rupt line at U114 pi...

Page 126: ...light pen circuits without a user supplied program to set up interrupts handle timing and take care of bit locations detected by the light pen As a result this discussion can only be general When the...

Page 127: ...s this by continually polling PA6 at U114 pin 8 This allows the Computer operator to do such things as move a dot around the CRT face with the light pen As before the Computer must be programmed to us...

Page 128: ...sserting pin 13 the IO line This signal comes from U224C pin 10 and goes low whenever the CPU asserts the S 100 slNP or sOUT lines Once lO is asserted U179 de codes the address at its inputs and selec...

Page 129: ...in 10 is asserted section B of decoder U157 is selected It decodes address lines BA2 and BA3 to enable one of the following ports 6821ACSS The parallel port U114 8253CS The timer port U160 EPCIACS Ser...

Page 130: ...4 12 Jumper wir 6 474 12 6 224 12 6 102 12 6 220 12 6 511 12 6 103 12 6 102 12 6 472 12 NOT USED 9 131 9 124 NOT USED 9 124 9 124 9 132 9 124 9 132 9 1 30 9 133 9 124 9 106 9 128 9 106 9 133 9 106 9 1...

Page 131: ...9 44 21 762 25 924 25 918 21 762 NOT USED 25 820 21 762 21 718 21 762 25 918 21 762 25 859 21 762 21 762 25 924 21 762 29 44 21 762 25 820 21 762 21 763 1 tLF ceramic 100 tLF electrolytic 1 p F cerami...

Page 132: ...Comp No Part No Inductors L101 L104 235 229 35 B H Transducers 473 29 Audio Transducer X101 Crystals 404 645 404 647 404 644 150 132 150 133 10 MHz 6 MHz 15 MHz 4 MHz 4 9152 MHz Y101 Y102 Y103 U191 U...

Page 133: ...in circuit board Component Number Index CIRCUIT COMPONENT NUMBER HEATH PART NUMBER 57 607 56 56 56 89 444 126 444 104 443 10S1 443 875 443 1014 443 791 443 970 443 791 443 973 443 1037 443 811 443 104...

Page 134: ...U203 U204 U205 U206 U207 U208 U209 U210 U211 U212 U213 U214 U215 U216 443 791 443 754 443 752 443 872 443 900 443 875 443 976 443 1081 443 1051 444 130 443 875 443 797 443 879 443 754 443 791 444 101...

Page 135: ...8 U229 U230 U231 U232 U233 U234 U235 U236 U237 U238 U239 U240 U241 U242 U243 U244 U245 U246 U247 U248 443 791 443 1112 443 900 443 755 443 875 443 728 443 791 443 1048 443 1049 444 105 443 837 442 644...

Page 136: ...B201 200 nS delay line 41 10 56 89 56 56 GD510 1N4149 IMPORTANT TNEOANDKO ENDOFDIODESCAA OK MARREDIN ANOMOER OFWAYS Diode 1N5817 56 607 SANDED END CAYFIODE THRESHOLD DISCHIYRGE J CONTROL Vcc VOLTAGE E...

Page 137: ...uffers 443 72 I 2 3 I 5 6 7 IA I Y 2A 2Y 3A 3Y GxiD CC 8 7 6 5 75452 Peripheral Drivers 443 74 I 2 3 4 GND 4A 4Y 38 3A 3Y I I I IG 9 8 Vcc 48 1 4 1 3 74LSOO Quad 2 input NAND 443 728 A 7 I A 18 I Y ZA...

Page 138: ...octal Buffer 74LS240 C D A B I 2 3 4 5 6 7 8 9 1 0 I G IA I 2A4 I A2 2Y3 IA3 2Y2 I A4 2YI GND Y6 A5 Y5 A4 Y4 1 2 11 1 0 9 8 Vcc A6 14 13 443 755 Hex inverter 74LS04 I 2 3 4 5 6 7 Al Yl A2 Y 2 A3 Y3 G...

Page 139: ...F 443 791 74LS244 3 state buffer driver C D A 8 I 2 3 4 5 6 7 8 9 1 0 IAI 2 A 4 IA2 2Y3 IA3 2Y2 IA4 2 YI G ND 4 A 4Y 38 3 A 3Y 1 2 11 1 0 9 8 12V 4 8 1 4 1 3 75188 TTL RS232 driver 443 794 I 2 3 4 6...

Page 140: ...LFAR 10 Vcr 4C 4A 4Y 3 C 3 A 3Y 1 4 1 3 1 2 1 1 1 0 9 8 D 74LS125 Quad 3 state buffer 443 811 I 2 3 4 5 6 I IA I Y 2C Z A 2Y GN D SELECT DATA OUTPUTS EBB LE Vcr 20 Z A 28 2 YO 2YI 2YZ 2Y3 16 I 1 4 1 3...

Page 141: ...te buffer 1 2 3 4 5 6 7 8 G l 1 A lY ZA 2 Y 3A 3Y GN D Vcc 1 C lY 3C 38 3 A 3Y 1 4 1 3 1 2 11 1 0 9 8 74LS11 Triple 3 input AND 443 864 1 2 3 4 5 6 7 1A 18 ZA 28 ZC 2Y G i sD Vcc A6 Y6 A5 Y5 A4 Y4 14...

Page 142: ...SELECT 6D 5 D 5 0 dD 40 CLOCK 14 1 3 1 2 11 1 0 9 V cc 6 0 1 6 1 5 D CK CLEAR D CK D CK C1EAR CLEAR 443 879 74LS174 Hex D flip flop LEAR CLEAR CLEAR CK CK CK 0 0 0 0 0 1 2 3 4 5 6 7 8 CLEAR 1Q 1D 2 D...

Page 143: ...443 948 I 2 3 4 5 6 I 8 ICK IK I J I PR 10 2 0 GN D VSS CA S 0 A6 A3 A4 A5 AT I o 1 5 1 4 1 3 IZ I I IJ 9 MCM6665 64K x 1 RAM 443 970 2 3 4 5 6 I 8 N C D V R A A O A 2 Al Vr e OUTPUTS 2 VCC ZA CL EAR...

Page 144: ...D OUTPUTS INPUTS ix o C z 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 8088 Microprocessor X D 443 1 009 1 2 3 4 5 6 7 8 9 10 11 1 2 1 3 1 4 15 16 17 18 19 20 c z z z o a a D I D CL x O o o o o...

Page 145: ...3 4 5 6 7 8 9 10 I l 1 2 13 ln Io r I n I N o o C O O O O O O C l O CO c Lr 0 I c c I Icc o o o o o o o o c o Icr o CCQ a O C cc Irr I rI w o N M r c I I I 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26...

Page 146: ...2YO 1 6 15 1 4 1 3 12 1 1 1 0 9 443 1036 74LS156 Dual 2 to 4decoder I 2 3 4 DATA STRB SELECT IY3 IC 1 0 I N P UT 8 5 6 IY2 IYI OUTPLITS 7 8 IYO GND INPUTS INPUTS OUTPUT OUTPUT OUTPUT YCC CQNTBQI 4A 4B...

Page 147: ...74ALS02 I 2 3 4 5 6 7 I Y I A 18 2Y 2A 28 GND Vcc I C 1 Y 3C 38 3 A 3Y 1 4 1 3 1 2 11 10 9 8 443 1047 74ALS10 Triple 3 input NAND A I 2 3 4 5 6 7 IA 18 2 A 28 2C 2Y G N D 48 4A 3Y 38 3A 1 2 l l 10 Vcc...

Page 148: ...5 6 7 1 CLR I D I CK I PR 10 I Q GiND RIPPLE OUTPUTS CARRY EiNABLE CC OUTPUT QA QB QC QD T L O AD 16 1 5 14 13 12 1 1 1 0 9 443 1054 74LS169 4 bit U D counter CARRY OUTPUT UP DOIc N RIPPLE QA 08 QC QD...

Page 149: ...O O Cl C5 H C3 U O Vcc 2D 2C h C 2B 2 A 2Y 1 4 1 3 1 2 II 10 9 8 443 1081 74ALS1020 Dual 4 input NAND buffer 5 6 7 IA 18 iVC IC I D IY Ci U D I 2 3 4 Vcc Cx2 Rx2 CD2 11 1 0 02 I i 1 5 14 1 3 1 2 11 1...

Page 150: ...tems or Heath Company Available only from Zenith Data Systems or Heath Company 444 104 Memory Decoder ROM System I O Decoder ROM UCC A7 CS2 CS 00 01 02 03 1 6 1 5 1 4 13 12 11 10 9 2 3 4 5 6 7 8 A6 A5...

Page 151: ...h Data Systems or Heath Company ROM address decoder HAL or PAL16L2 AiVD GATEARRAY 1 2 3 4 5 6 7 8 9 1 0 PAL 14L4 20 19 1 8 1 7 16 15 1 4 1 3 1 2 11 444 130 Available only from Zenith Data Systems or H...

Page 152: ...S B BCYC F CAS C WE RREQ WO MD GATE GND 8 PHANTOM LOGIC EQUATIONS RASO RAS1 RAS2 CAS A CAS B CAS C WE MDGATE RENO TAP1 RENO STC RREQ BCYC TAP1 REN1 TAP1 REN1 STC RREQ BCYC TAP1 REN2 TAP1 REN2 STC RREQ...

Page 153: ...INOU2 OUT2 85HOLD HOLD GND F LOGIC EQUATIONS SS HOLD pHLDA 88SEL OUT3 OUT2 85HOLD 85HLDA SSEL INOU3 HOLD HOLD 85HLDA 88HLDA SSEL I NOU3 85HLDA SSHLDA 85HLDA SSHLDA 85HLDA SSHLDA SSEL INOU3 85HLDA 88H...

Page 154: ...TION 444 129 1 Top 32K Selector VCC A12 A A13 MEMR A14 ROM1 A15 A16 u NC ROMSEL A17 A18 g ROMO A19 0o A23 A20 A22 A21 GND p LOGIC EQUATION ROMSEL ME M R R O M O ROM1 MEMR ROMO ROM1 A15 MEMR ROMO ROM1...

Page 155: ...ecoder VCC BA18 BA19 BCYC g TAP2 BA20 DEC ODEN BA21 a V CLRRR BA22 BA23 CLRMR MA PSELO F D I EN MAPSEL1 00 u PHANTOM TA P1 MDENB DBIN GND o LOGIC EQUATIONS BA18 BA19 BA20 BA21 BA22 BA23 DBIN MDENB PHA...

Page 156: ...09 OOOA OOOB OOOC OOOD OOOE OOOF 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 db db db db db db db db db db db db db db db db db db db db db db db db...

Page 157: ...db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of...

Page 158: ...b db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of...

Page 159: ...OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF db db db db db db db db db db db db db db db db db db db db db db db...

Page 160: ...db db db db db db db db db db Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Of Reserved f o r Reserved f o r R...

Page 161: ...IDENTIFICATION IODEC 1 0 decoder for the Z 100 O ODB O F O ODC O F D ODD O F O ODE O F O ODF O F db db db db db page Of Of Of Of Of Video 68 a2 1 por t Video 68 a4 5 C R TC Video 68 a4 5 CR TC Video l...

Page 162: ...05 Of Of Of Of Of Oe Oe Oe Oe 06 68a21 Pri n t e r p o rt 68a21 Pr inter p o r t 68a21 Pri n t e r p o r t 68a21 Pri n t e r p o r t 8253 T i me r por t 82 53 T i me r por t 8253 T i me r por t 8253 T...

Page 163: ...page 2 125 SEMICONDUCTOR IDENTIFICATION IODEC E 0 decoder for the Z 100 Macros Symbols No Fatal er r or s...

Page 164: ...PUTS ARE AS FOLLOWS MAPSEL1 MAPSELO BA17 BA16 BA15 BA14 BA13 BA12 A7 A6 A5 A4 A3 A2 A1 AO PROM OUTPUTS ARE AS FOLLOWS BSEL PI N 9 MS B REN2 REN1 REND PI N 1 2 L S B 03 02 01 00 1 MAP 0 DB DB DB DB DB...

Page 165: ...2C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB OF...

Page 166: ...6 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 005 8 0059 005A 005B 005C 005D 05 05 05 05 05 05 05 05 05 05 05 05 06 06 06 06 06 06 06 06 06 06 06 06 06 06 06 0...

Page 167: ...05 05 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 05H 05H 03H 03H 03H 03H 03H 03H 03H 03H 03H...

Page 168: ...05 05 05 05 05 05 06 06 06 06 06 06 06 06 06 06 06 06 03 03 03 03 DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F DB DB...

Page 169: ...OBO OOB1 OOB2 OOB3 OOB4 OOB5 OOB6 OOB7 OOB8 OOB9 OOBA OOBB OOBC OOBD DOBE OOBF HAP 3 1 OOCO OOC1 OOC2 OOC3 OOC4 OOC5 OOC6 OOC7 OOCB OOC9 OOCA OOCB OOCC OOCD OOCE OOCF 06 05 05 05 05 05 05 05 05 05 05...

Page 170: ...DB DB DB DB 06H 06H 06H 06H 06H 06H 06H 06H 06H 06H 05H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H 03H OOEO OOE1 OOE2 OOE3 OOE4 OOE5 OOE6 OOE7 OOE8 OOE9r OOEA OOEB OOEC OOED OOEE OOE...

Page 171: ...page 2 133 SEMICONDUCTOR IDENTIFICATION...

Page 172: ...00 0003 49 0004 05 0005 91 0006 Ao 0007 83 0008 49 0009 09 O OOA 00 OOOB 01 O OOC 83 O OOD 91 O OOE AO O OOF 05 0010 05 0011 09 0012 00 0013 49 0014 05 0015 11 0016 20 0017 03 0018 49 0019 09 001A 00...

Page 173: ...SEMICONDUCTOR IDENTIFICATION ver 2 CPU Status Decode Rom for the Z 100 db 00000011b db 00010001b 30 db 00100000b db 00000101b end 03h 11h 20h 05h 88 sINTA 88 sINP 88 sOUT 88 sHLTA 001C 03 001D 11 001E...

Page 174: ...eplacement part A Fi nd the circuit component number R5 C3 etc on the X Ray View B Lo cate this same number in the Circuit Component Number column of the Parts List C Ad jacent to the circuit componen...

Page 175: ...C107 CI 8 C1 0 9 e 8 8 8 41 I7 19 OI PIS I O 0 C I 31 C166 C16 C165 0 4l ID O R108 7 C174 I CI74 R109 88 C186 m Ik 019 O C Ik O Al O 4 17 213 0 0 R I 99 0208 4 C209 Al O N 0 4 x C 210 MAIN CIRCUIT BO...

Page 176: ...C114 R101 C113 C115 C119 kg p CV P191 4 4 i o e Z 2 C113 1 Z Z 6131 0 C198 U229 0 Q 4 p 0c p p III 0206 p 0 0 C2 0 0 ok W 4 MAIN CIRCUIT BOARD Component side shown in red foil side shown in gray...

Page 177: ...a Request to send Clear to send Data set ready Signal ground common return Received line signal detector Reserved for data set testing Reserved for data set testing Unassigned Secondary received line...

Page 178: ...t clocks data Data to the peripheral Data to the peripheral Data to the peripheral Data to the peripheral Data to the peripheral Data to the peripheral Data to the peripheral Data to the peripheral Ac...

Page 179: ...keyboard cable connectors Connector P105 PIN SIGNAL NAME FUNC TION 1 2 3 4 5 6 7 8 9 10 COL15 CTRL COL8 KBRST COL12 COL14 COL9 COL13 COL4 COL10 COL1 COL5 COL3 COL11 COLO COL2 COL6 COL7 LED ANODE LED C...

Page 180: ...or P107 PIN SIGNAL NAME FUNC TION 1 4 5 6 7 2 3 SHIFT ROW CTRL RESET ROWO ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 Shift row line Control CTRL and RESET line Row 0 line Row 1 line Row 2 line Row 3 line Row...

Page 181: ...AL NAM E FU NC T IO N 1 4 5 6 7 2 3 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 9 10 5VDC 5VDC 5VDC 5VDC GND GND GND GND BAO BA1 BA1 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12...

Page 182: ...06 BD07 GND GND BDIO BDI1 BDI2 BDI3 BDI4 BDI5 BDI6 BDI7 RDBFRENBL NC GND GND CRTRAMSEL VIDRAMRDY LTPNSTB POC RES ET2 ECLK OUT OUT MEMR Ground Ground Data input lines Ground Ground Ground Ground Data o...

Page 183: ...71 72 73 74 75 76 77 78 79 80 STVAL SYNC BMWRT WO WR IO DBIN VI DINT GND GND GND GND Status valid signal Buffered memory write Status write Write strobe Chip select line Data request control signal V...

Page 184: ...1 GND 2 GND Ground Ground No connection Plus 5 volt supply Plus 5 volt supply Plus 5 volt supply Plus 5 volt supply Ground Ground 5 5 6 5 7 5 8 GND 9 GND Connector P102 PIN SIGNAL NAME FUNCTION Ground...

Page 185: ...Page 3 1 Keyboard Encoder 3 2 Description User Options and Programming Theory of Operation Troubleshooting Keyboard Scan Matrix Encoder Output Codes hex Keyboard Key Layout 3 11 3 10 3 12 3 3 3 8 3 19...

Page 186: ...functions that the keyboard encoder provides are Au torepeat on off 11 keys per second when selected Fa st repeat rate 28 keys per second Key debounce 5 milli seconds maximum Ke y click on off Cl ear...

Page 187: ...n the event driven mode a click is produced when a key is pressed and another click is produced when the key is released FIFO The keyboard encoder maintains a 17 key FIFO first in first out buffer in...

Page 188: ...ignored by the keyboard encoder Illegal commands will also be ignored by the encoder Input Data From Keyboard Encoder Key codes are the only information which may be read from the data port There are...

Page 189: ...n of the keyboard The bits of the status port are de fined as follows STATUS REGISTER D7 D6 D4 D3 D2 D1 DO D5 KDA undef u n def und ef und ef und ef und ef KPR Keyboard Data Available 1 Character Avai...

Page 190: ...ot clear the data register of the keyboard processor The only way to do this is by reading the data register AUTOREPEAT ON Enables the autorepeat function Auto repeat causes a key to be repeated when...

Page 191: ...causes a different scanning algorithm to be used suchthata code isgenerated when a key isdepressed and another code is generated when the same key is released Each key has a unique code including CTRL...

Page 192: ...ns of the keyboard See Pictorial 3 1 When one of these output lines at P105 goes low then any key closure of a key attached to that particular column will be detected as the keyboard encoder IC scans...

Page 193: ...oa OO 0 a 0 0 o 5 N t gn D IL D G 0 z U 2 2 0 DJ t4 tUd U a t D Z D n O Lt n a Jt I Lt 0 N 0 I I 0 Q 0 N IO IO U d d O Ottt 0 0 N 5 0 4 IJ 0 ND tD O a d d 0 0 IJO U 0 0 0 X X N 0 IIJ ILI IIJ 0 0 N IJ...

Page 194: ...reoccur Refer to the Circuit Board X Ray Views for the physical loca tion of parts on the circuit boards POSSIBLE CAUSE PROBLEM Keyboard does not function 1 Keyboard in disabled mode RESET the Comput...

Page 195: ...Page 3 11 KEYBOARD SCAN MATRIX Pictorial 3 1 shows the keyboard scan matrix how the keys are positioned electrically C tU K O O n CT CC R a Pictorial 3 1 Keyboard Matrix...

Page 196: ...difiers such as the A key In the following table an NC under a modifier indicates that no code is generated for that key The CAPS LOCK column has a Y yes or N no to indicate if the CAPS LOCK key affec...

Page 197: ...ode 5 35 25 35 25 53 D3 36 5E 36 1E D2 52 37 26 37 26 D1 51 38 2A 38 2A DO 50 39 28 39 28 5A DA 61 41 01 01 07 87 62 42 02 02 13 93 63 43 03 03 15 95 64 44 04 04 05 85 65 45 05 05 OD 8D 66 46 06 06 04...

Page 198: ...4E OE OE 12 92 0 6F 4F OF OF 19 99 70 10 10 1A 9A 50 71 51 OF 8F Q 52 12 12 OC 8C 72 73 13 13 06 86 53 74 14 14 OB 8B 54 75 15 15 09 89 55 56 16 16 14 94 76 W 57 17 17 OE 8E 77 78 58 18 16 96 18 79 19...

Page 199: ...Caps Lock Yes No Down Code Up Code Key 1B 1B 1B 1B 4F CF ESC 20 20 20 20 45 C5 SPACE 27 22 48 C8 27 3C 2C 3C 4D CD 2C 5F 2D 1F 5C DC 2D 3E 2E 3E 4A CA 2E 3F 2F 3F 4B CB 2F 3A 3B 3A 49 C9 3B 2B 3D 2B 5...

Page 200: ...C2 DELETE 8D CD 8D CD 38 88 ENTER HELP D5 95 C5 46 C6 95 FO D6 96 D6 27 A7 96 F1 D7 97 D7 26 A6 97 F2 D8 98 D8 25 A5 98 F3 99 D9 D9 24 A4 99 F4 DA 9A DA 23 A3 9A 98 DB 98 DB 22 A2 F5 F6 9C DC 9C DC A...

Page 201: ...arrow left arrow A4 A7 A6 A5 A8 E4 E5 E8 E6 E7 A4 A5 A6 A7 E5 E4 E6 E7 E8 2F 3B 33 3A 3F AF BB B3 BA BF A8 HOME A9 E9 A9 E9 B7 37 BREAK keypad keypad 0 keypad 1 keypad 2 keypad 3 keypad 4 keypad 5 ke...

Page 202: ...wn Code Up Code Key B7 F7 B7 F7 36 B6 7 keypad 8 keypad 9 keypad B8 F8 F9 B8 B9 F8 F9 3E 32 BE B2 B9 NC NC NC NC 60 EO FAST REPEAT NC NC NC NC 61 E1 CAPS LOCK SHIFT right NC NC NC 62 E2 NC NC NC NC NC...

Page 203: ...ws the key layout of the keyboard 0 RESET F2 FT FS FS FM FH F12 0 CHR I CHR OEL LINE INS LINE HOME FO F I ESC S 4 Xi Q e 8 0 X 5 6 HELP TAS Q W E R T Y U I 0 P SELTTE CRPS CTRL A 5 D F G H J K L j z Q...

Page 204: ...Theory of Operation Programming Data Circuit Description Troubleshooting Replacement Parts List 4 29 4 48 4 69 4 3 4 5 4 70 4 72 Semiconductor Identification Circuit Board X Ray View 4 106 Interconnec...

Page 205: ...e with RGB type color monitors The normal display format is 25 rows of 80 characters with each character consisting of an 8 wide by 9 high character cell However as the video board uses bit mapped pix...

Page 206: ...4 BL1 E I J8 Ieg e r Iitr 3 0 Q e t 1 i IIIIMit II t 4 kit yC I 3 32 1 1324 233 32 t t litI i 1 2 J305 J 3 0 6 I J304 1 t 3 J3 1331 331 u33 Lij LOW 33K e J307 1 2 t 33 31 1 2 37 P 383 7 1 14 17 I 3 7...

Page 207: ...INSET I CHARACTER 01234567 1 9 CHARACTER SCA N LINE LINES COI 0 0 1 2 3 225 HCR IZONTAL SCAN I INES 24 PICTORIAL 4 2 Video Display...

Page 208: ...jumper on the marked side selects positive polarity H is the normal position J303 S e lects either composite sync or vertical sync for the external RGB monitor Placing the jumper on the V marked side...

Page 209: ...K type RAM chips are selected 3 If no jumper is installed upper type 32K RAM chips are selected Black Level Control This control R307 should be set initially at the 1 o clock posi tion as shown and th...

Page 210: ...ee the inset drawing The result of this grouping is 25 character lines on the screen 225 9 25 Each of the 25 character lines can display 80 characters As shown in the inset drawing each character is m...

Page 211: ...will be prop erly displayed on the screen along with any other characters that have been entered Color Display To produce color a separate memory plane array of video RAM is used for each of the thre...

Page 212: ...levels of intensity brightness can be produced which corresponds to the above colors White is the most intense and black is the least intense Light Pen The light pen is a light detector rather than a...

Page 213: ...cter line display that has 9 scan lines per character line and 80 characters per character line The microprocessor places a byte of data in the 2K x 8 char acter RAM for each character on the screen 8...

Page 214: ...0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 9 DATA BYTES IN ROM DISPLAY SCREEN 24Q 1 BIT REVERSE VIDEO FROM M IC ROPROCES SOR 2K x 8 CHARACTER RAIVI CHARACTER GENERATOR ROM 128CHARACTERS 8 8 IT PARALLEL...

Page 215: ...D BLUE GREEN 64K OR 32K x 8 RAM GREEN SHIFT REGISTER RED S H IFT R E GISTER BLUE SHIFT REGISTER MICRO PROCESSOR 16 BIT COUNTER 12 B IT COUNTER 4 B IT COUNTER CRT C PICTORIAL 4 4 Add Memory And Counter...

Page 216: ...scan lines of the first character row are displayed Then the 4 bit scan line counter starts over and the 11 bit character counter selects the next character row in memory This continues until all the...

Page 217: ...0 x 25 x 9 18000 bytes When a program prints a character all nine bytes of the char acter s font pattern are looked up in memory and stored in the 32K x 8 video RAM Color is achieved by superimposing...

Page 218: ...of CPU address memory that is not used is Area B The RAM mapping mod ule changes the CPU addresses intoa more compact se quence such that only the Displayed Area data of Pictorial 4 6 is placed in vid...

Page 219: ...dress Bits 0 through 3 called R3 RO make up the scan line counter and bits 4 through 15 the memory refresh address MA11 MAO select the bytes that make up the scan line when the screen is refreshed The...

Page 220: ...HIFT REGISTER BLUE 5 H IF T RE G IISTER VIDEO RAIVI MA PP I NG MODULE C D VRAMA8 VIDEO 5 I GNALS Data to he displayed 8808 pP C D CRT C C D SYNC 5 I GNA LS MON ITOR LIGHT PEN C D CONTROL DATA LINES D...

Page 221: ...B 3 In a system with 64K RAM s installed areas A and B are addressed by setting the address latch to 80H assuming the start address is 98 wrap back into the displayed 32K space CRT C MAPPED ADDRESS SP...

Page 222: ...Pixel 3rd Pixel 4th Pixel 5th Pixel 6t h Pixel 7th Pixel 8th Pixel 9th Pixel 1st Pixel 1st Char Column Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 1280 1281 1282 2nd Char Column 16 17 1...

Page 223: ...een ripple Scrolling is achieved by adding 1280 bytes 80x16 to the start address The CRT C begins refreshing the screen from what would normally be the second character line but displays those charact...

Page 224: ...12 13 14 15 16 17 1B 19 20 21 22 23 24 25 9 10 LINES NOT DISPLAYED H OR I2ONTAL SCAN LINES 11 12 13 14 15 16 17 224 391 392 393 399 223 224 Pictorial 4 8 Scan Line And pixel Numbering Using the physi...

Page 225: ...effectively multiplies the X value by 16 In Pictorial 4 9 the X coordinate is shown split into two pieces to emphasize that both parts are subsequently treated differently Since the number of bytes pe...

Page 226: ...ICAL SCREEN ADDRESS y x 15 7 6 11 10 8 7 4 3 15 15 8 7 MA PP ING ROM BASE ADDRESS 7 0 8 8 IT ADDER CRT C x HORIZONTAL BYTE INDEX 0 127j y VERTICAL BYTE INDEX D 511 PICTORIAL 4 9 Video RAM Mapping Modu...

Page 227: ...0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 00 O OH 0 1 01H 0 2 02H 0 3 03 H 0 4 04H 1 0 0 8 H 1 1 09H 1 2 O A H 1 3 O B H 1 4 OCH 2 0 10H 2 1 11H 2 2 12H 2 3 13H 2 4 14H 3 0 18...

Page 228: ...value input It also shows that once all the legal input address es have been assigned to their corresponding sequential out put addresses the remainder of the physical or CRT C RAM addresses are assi...

Page 229: ...since it in fact is the old rep resentation for character line 2 It is important to understand that data itself does not move For this reason the last line on the screen may be in what now is scrambl...

Page 230: ...based on the start address All references to a particular line of data are fixed with respect to the 8088 Furthermore since the video RAM mapping module is between the 8088 and video RAM its operation...

Page 231: ...the following x marked pixel would be one 0000000X Similarily 85 55 hex would turn on the following pixels OXOXOXOX To display the pixel in the upper left hand corner of the screen 128 80 hex would b...

Page 232: ...of intensity are avail able with all the video RAM installed Each level of intensity corresponds to one of the possible colors previously men tioned white is brightest and black is darkest no pixels...

Page 233: ...the green plane also But if only the green plane is written to only the green plane will be changed Also the write bits have no effect on the read opera tions of any plane Write bits can be used to p...

Page 234: ...ry The light pen is actually a light detector It detects light and provides a pulse compatible with the logic used in the Com puter If this pulse is used to latch the position where the light pen hit...

Page 235: ...e going pulse An add itional inverter is provided U134 D in case the pen generates a positive going pulse J103 is a 3 pin jumper which selects the positive or negative going pulses The positive going...

Page 236: ...RAO RA3 Hence on the occurrence of PENSTBD these four bits will be clocked into U315 which can be read out by software The information is available on the most significant nibble D4 D7 U324 is a count...

Page 237: ...for 80 characters per row dividing the character position by 80 the quotient and remainder will tell us the row and the character number within that row where the light pen hit occurred OADH 50H 173 8...

Page 238: ...d Recall that we mentioned earlier that a correction is needed to be done on the number we get by subtracting START ADDR from LIGHT PEN ADDR This is due to the fact that a definite amount of delay is...

Page 239: ...ta toward the end of this Manual The following chart lists the port addresses for devices that are located on the video logic circuit board A more complete list can be found in the Programming Data se...

Page 240: ...VRAM The lower four bits D3 DO have nothing to do with VRAM access but instead control what is displayed on the screen That is they control the data com ing out of the VRAM that is applied to the pix...

Page 241: ...e 1 Turns off green plane D2 0 Enables blue plane 1 Turns off blue plane D3 0 Enabled planes appear bright 1 Data from VRAM are displayed Port Address ENABLE ENABLE ENABLE VRAM W R T WRT WRT ENABLE BL...

Page 242: ...ng chart shows how the video display control bits D3 DO of port D8 can control the screen display D3 D2 D1 DO EN EN EN FLASH BLU GRN RED 0 0 0 0 1 0 0 1 0 1 0 0 1 0 The screen a p pears white no matte...

Page 243: ...anes black 0 1 1 0 1 Green plane is enabled are enabled VRAM data appears enabled VRAM data ap 0 1 1 Blue plane is enabled VRAM data appears 1 0 0 Green and red planes are enabled VRAM data appears VR...

Page 244: ...ned on and VRAM data is masked Those planes enabled will ap pear DO D2 1 so the red and blue planes are turnedoff D1 Osothe green plane is enabled and the screen is green Exam le 2 D3 D2 D1 DO EN EN E...

Page 245: ...ch When D7 1 VRAM is turned off D6 D4 have no effect on VRAM access and the CPU will not be able to read from or write to any plane red green or blue When D7 0 video RAM is enabled This is the normal...

Page 246: ...ify two corresponding mem ory locations in two color planes red and green 1 Lo c ation OE68CO is in the green VRAM Therefore no matter what bits D6 D4 are green VRAM location OE68CO will be modified t...

Page 247: ...on in the other blue plane since blue is in the C page Write FF hex to location OC0000 hex The above three steps produce the desired results but a slightly better scheme avoids the work of keeping tra...

Page 248: ...0 0 0 port D8 hex 08 hex alphanumeric mode For some graphic applications where you do not want to write to more than one plane at a time the value would be 0 1 1 1 1 0 0 0 78 hex port D8 hex 78 hex gr...

Page 249: ...bits D7 and D6 don t care and R13 is the low byte R12 and R13 are read write registers Example Read the low byte of the start address register MOV AL OODH OUT ODCH AL IN AL ODDH In the mapping scheme...

Page 250: ...4 SHR AX CL OUT ODAH AL How to Turn Pixels On and Off Refer to the Theory of Operation on Page 4 5 for a detailed description of how the video section works The most significant bit MSB of any given b...

Page 251: ...seven bits define the byte position in a given line with 00 being the left most The most significant nine bits define the line address with 000 being the top most line A15 A14 A1 3 A 1 2 A 1 1 A 1 0...

Page 252: ...s space Holes refer to locations that do not appear The actual screen will be continuous For example when the CRT C is programmed for 9 scan lines line 10 hex will appear immediately below line S hex...

Page 253: ...ex OD refers to the character row number and 2 refers to the scan line number within the character row Since the CRT C has been programmed for nine lines per row of characters the location will corres...

Page 254: ...X The X coordinate is the twenty eighth byte and the Y coordi nate is the third row and the fifteenth line in that row Since the CRT C will display only 9 scan lines line E hex the 15th line will not...

Page 255: ...bility is invoked and whether or not FLASH or any planes are enabled Activating clear screen can wipe out all red green and blue VRAM locations Ports D9 hex and DB hex control ports A and B are reada...

Page 256: ...READ modify and WRITE sequence IN A L ODBH AND AL OFVH OUT ODBH AL 4 Write a zero into bit 3 of port D9 hex This will activate CLRSCRN 5 Wa i t for 16 7 milliseconds in the 50 Hz mode this wait is 20...

Page 257: ...et the color of the screen to the planes enabled 3 Write a 1 into bit 3 of port DB hex This will make SET 1 4 Write a 0 into bit 3 of port D9 hex This will make CLRSCRN 0 5 Wa it for 16 7 mS or 20 mS...

Page 258: ...rs to their initial conditions on power up or reset 6845 Chip selects the CRT C for accessing the in ternal registers ECLK Latches the data into or out from the registers on its trailing edge BAO Help...

Page 259: ...port ODCH This is coupled through U338 to the data lines of the CRT C At this time 6845CS at VIOSEL U369 asserts the chip select line at pin 25 of the CRT C Since the port address is ODCH line BAO 0 t...

Page 260: ...address by ten to point to the next character line For each address a byte is read from video RAM VRAM and shifted serially out to the video amplifier with the horizontal and vertical sync pulses The...

Page 261: ...Char 1st Char 1st Char 1st Char 1st Char 1st Char 1st Char 1st Char 2nd Char 1st Pixel Row 2nd Pixel Row 3rd Pixel Row 4th Pixel Rov 5th Pixel Row 6th Pixel Row 7th Pixel Row 8th Pixel Row 9th Pixel...

Page 262: ...ICs can get refreshed during a normal CRT C scan in both the non interlace and interlace modes This results in a reduc tion of components in the video circuits Jumper J307 permits the use of 64K RAMs...

Page 263: ...addressed data settles VIDSTRB from U376 pin 17 asserts to latch and RGB data into U332 U302 and U311 Note If this is a minimum system green only U332 and U311 outputs will remain a steady state Next...

Page 264: ...d by two character clocks through the hex D flip flop This delay is used to match the timing of DISEN to the video signal delayed by the parallel in serial out converters If DISEN wasn t delayed retra...

Page 265: ...1 2 and 3 If this is a minimum system green only pins 1 and 2 are jumpered to pin 3 U323 decodes the three inputs to assert only one output at QO Q7 This signal connects to U309 and is clocked throug...

Page 266: ...ce U322 pin 6 at logic zero This lowers Q301 s emitter voltage to the black level Composite sync from U355 pin 11 provides horizontal and vertical sync pulses at the blacker than black level The compo...

Page 267: ...logic The out puts are 6845CS Selects the CRT C programming as described earlier CRTIOCS A Chip selects the PIA at U345 and B provides one input to the OR gate U372 U366 The other input to this OR gat...

Page 268: ...the selected video line without affecting RAM FLASH causes the selected line to appear as a solid color See Converting RAM Data to Video Page 4 53 for more information WRT R WRT G WRT B Provides a s i...

Page 269: ...at location in the video memory map is selected See Pictorial 4 11 RSEL ODOOOOH ODFFFFH GSEL OEOOOOH OEFFFFH BSEL OCOOOOH OCFFFFH FFFFF F0000 EFFFF EOOOO DFFFF DOOOO CFFFF COOOO BFFFF BOOOO AFFFF AOOO...

Page 270: ...memory when it is accessing video RAM This permits you to install read write memory in the same address space as VRAM without them interferring with each other CRTRAMSEL also goes to U372 pin 3 VIDRAM...

Page 271: ...365 It translates the CPU address range into the address range used by the CRT C The CRT C sees the VRAM in the range of 0 64K while the CPU sees the memory in the range of 768K to 960K To convert the...

Page 272: ...U351 pin 4 The RAS portion of the address is present on VAO VA7 U350 gates the RAS line through U375 pin 11 U375 pin 8 and U374 pin 8 for the selected bank Next the CAS address is placed on VAO VA7 an...

Page 273: ...CPU to quickly clear the screen Instead of directly writing to memory which is time consuming the CPU uses the fast scanning feature of the CRT C Here s how The CPU asserts the CLRSCRN line at the PI...

Page 274: ...Page 4 64 CIRCUIT DESCRIPTION QD Q05 Q10 Q15 Q25 Q30 Q35 QPD Q55 Q60 Q65 Q70 CRT C CRT C CPU RAS ADMUX CAS VID STROBE CPU STROBE CCK1 LOAD S R CCK2 Pictorial 4 12 Video Board Timing...

Page 275: ...te the odd numbered waveforms from Q05 to Q65 These signals connect to the VIDRAM PAL at U376 U376 uses the Q signals to generate VIDSTRB ADMUX RAS and CAS VIDSTRB clocks addressed data into the latch...

Page 276: ...until the CPU RAS cycle begins At this time P305 pin 62 goes high to activate the CPU Obviously the CPU processing time will slow down if it per forms a lot of reading and writing to video RAM Howeve...

Page 277: ...2 of U361 When the CRT C has completed processing the video circuits Q15 at U361 pin 3 goes high This latches U361 pin 6 to logic zero and because U361 pin 9 is also zero drives the VIDRAMSEL line at...

Page 278: ...ata sheets Also the output of U356 pin 5 PENSTBD goes to U315 pin 11 U315 is an octal latch that is loaded by the CRT C row address lines RAO RA3 and the 4 bit down counter U324 At the time of PENSTBD...

Page 279: ...ed with it Remember to locate and correct the cause when components are dam aged or the problem could reoccur Refer to the Circuit Board X Ray View for the physical loca tion of parts on the circuit b...

Page 280: ...be in all units 1000 tt resistor pack 10 kt I resistor pack 1000 tt 4700 t t resistor pack 47tt 4700 t t resistor pack 1000 1 t 33 t t resistor pack 27tt 33 t t resistor pack 100 t t control 1000 t I...

Page 281: ...lectrolytic 1 rr F ceramic 10 p F electrolytic 1 rr F ceramic 10 pF electrolytic 1 p F ceramic 47 p F electrolytic 1 p F ceramic 180 pF ceramic C301 C302 C303 C304 C305 C307 C308 C309 C335 C336 C337 C...

Page 282: ...uit board CIRCUIT COMPONENT NUMBER HEATH PART NUMBER 417 118 417 118 443 892 443 805 443 892 443 1106 443 1106 443 1106 443 791 443 967 443 805 443 837 443 837 443 1 1 06 443 1106 443 1106 443 863 443...

Page 283: ...43 799 443 799 443 799 443 1057 443 1051 443 1051 443 799 443 855 443 855 443 754 443 1053 443 103 443 127 443 102 443 1049 443 1057 443 1049 443 1049 444 114 443 1048 443 1051 443 1045 U336 U337 U338...

Page 284: ...TH PART NUMBER MAY BE REPLACED WITH DESCRIPTION LEAD CONFIGURATION Vcc 2G I YI 2A4 I Y2 ZA3 I Y3 2AZ 20 1 9 1 8 1 7 1 6 1 5 14 1 3 IY4 2 AI 1 2 11 F E H G 443 754 74LS240 Tri state octal buffer B C J...

Page 285: ...5 6 7 IA 18 2 A 28 2C 2 Y GN D INPUTS INPUTS Vcc STROBE 4A 48 4 Y 3A 38 16 15 1 4 1 3 1 2 11 IQ OUTPUT OUTPUT 3Y 9 443 799 74LS157 G 4A IIB 4Y 3 A 38 5 3Y A 1 8 I Y 2A 28 2Y Quad 2 line to 1 line Mult...

Page 286: ...19 1 8 1 7 1 6 1 5 14 1 3 1 2 11 0 H D G OE D GQ G OE 0 F D OE D E Q G OE 74LS373 Octal D latch 443 837 0 A D OE D 8 0 G OE 0 D Q G OE Q C D G OE 3 4 5 6 7 8 9 1 0 ID 2D 2 0 3 Q 3 D dD d Q GND I 2 OU...

Page 287: ...CLEAR D CK CLEAR D CLEAR CKQ Hex D flip flop L CK 0 CLEAR CK CK D I 2 3 4 5 6 7 3 CLEAR IQ I D ZD 2Q 3D 3 0 G ND 4 A 4Y 38 3 A 3Y 1 2 11 1 0 9 8 Vcc 48 1 4 1 3 443 891 74LS86 Quad 2 input Exclusive OR...

Page 288: ...1 1 0 9 8 443 967 7406 Hex inverter I 2 3 4 5 6 IA I Y ZA 2 Y 3A 3 Y G ND V C C 4 O 16 1 5 4 O 4D 3D 3 0 3 O CLOCK 1 4 13 12 11 1 0 9 LR Q Q CK p Q Q CLR p CK 443 983 Quad D flip flop 74S175 CK p Q Q...

Page 289: ...a c m M u w c C C W W ct C W W c cc co a c cc cc c c c c c a cc c co cL CL 6 cL 0 cc c c cc cc c c a cc c L cc 4 8 4A 3Y 38 3A 1 2 11 1 0 9 8 Ycc 4Y 1 4 13 443 1045 74ALS02 Quad 2 input NOR D 443 1048...

Page 290: ...Y ENAHIE 8 C OD I L OAD CC OUTPUT A I 15 14 1 3 I Z 11 1 0 9 443 1054 74LS169 Up down counter R IPPLE CARRY OUTPUT UP DOY N CK A 08 OC OD ENABLE T LOAD ENABIE 8 C D P n I 2 U D CK 3 4 5 6 8 A B C EN i...

Page 291: ...or Heath Company Available only from Zenith Data Systems or Heath Company Video I O decoder Video memory decoder CC A7 1 6 1 5 CS2 CSI 1 4 13 00 01 02 03 12 I 10 I 2 3 4 5 6 7 A6 A5 A4 A3 AO Al A2 GI...

Page 292: ...24 23 22 2 1 20 1 9 18 1 7 1 6 1 5 14 1 3 444 127 Available only PROM from Zenith Data Systems or Heath Company PROM 256x 8 18S22 2 3 4 5 6 7 8 9 IP 11 1 2 A A A A A A A A 0 0 0 GNP 7 6 2 l 1 9 1 8 1...

Page 293: ...ler VCC QD Q05 co V I DRAM SEL Q10 Q15 V ID STR B Q25 a ADMUX CAS Q30 F RAS Q35 Q70 Q40 oo Q65 Q55 Q60 GND 8 LOGIC EQUATIONS RAS CAS ADMUX VIDSTRB Q30 Q55 Q05 Q30 QO Q60 Q25 Q70 VIDRAMSEL Q40 Q65 Q15...

Page 294: ...ENBLB NC FLASH BOUT DISEN u GOUT CURSOR ROUT RIN C G N B BIN A GND o LOGIC EQUATIONS ROUT GOUT DISEN ENBLR FLASH DISEN ENBLR CURSOR RIN DISEN ENBLR CURSOR RIN DISEN ENBLG FLASH DISEN ENBLG CURSOR GIN...

Page 295: ...OUTO INO OUT1 OUT2 IN2 OUT3 IN3 v IN4 OUT4 IN5 F OUT5 IN6 co OUT6 r OU T7 IN7 SET GND 8 LOGIC EQUATIONS OUTO CLRSCRN INO CLRSCRN SET OUT1 CLRSCRN IN1 CLRSCRN SET OUT2 CLRSCRN IN2 CLRSCRN SET OUT3 CLRS...

Page 296: ...0007 0008 0009 OOOA OOOB OOOC OOOD OOOE OOOF 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F OF OF OF OF OF OF OF OF OF OF OF OF 06 OC OA OF OF OF OF OF OF OF OF OF OF...

Page 297: ...b db db db db db db db db db db db db db db db db db db db db db db db Ofh Ofh Ofh Ofh Ofh Ofh Ofh 0fh Ofh ofh Ofh Ofh Of 1 Ofh Ofh 0fh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh Ofh...

Page 298: ...0077 0078 0079 007A 007B OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF db db db db db db db db db db db db d...

Page 299: ...b db db db db db db db db db db db db db db db db db db db db db Ofh Ofh 0 f 11 Ofh Of h Ofh Ofh Ofh Ofjl Ofh Of h Ofh Of 11 Ofh Ofh Ofh Of h Ofh Ofh Ofh Qf 11 Qfh Ofh Ofh Ofh Ofh Ofh Ofh Ofh 0th Ofh...

Page 300: ...5 OOD6 OOD7 db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db Ofh Of h Ofh 0 f h Ofh Ofh Qfh 0 f h 0 f h 0 f h 0...

Page 301: ...b db db db db db db db db db db db db db db db db db db db db db end nf 1 Ofh Ofh Ofh nfh nfh Ofh nfh nfh 0 f 1 nfh nf l Ofh nfh nf 1 nfh nfh Ofh 0 f h nfh 0 f h nfh 0 f h Ofh 0 f 1 0 f h 0 f h nf 1 0...

Page 302: ...page 4 92 SEMICONDUCTOR IDENTIFICATION VRAMSEL video ram select prom for the Z 100 Macros Symbols B LU EN 000 6 GRN E N O OOA RED E N O O OO No Fatal er r o r s...

Page 303: ...OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db Oofh oofh Oofh 00fh Oofh 00fh 00fh 00fh oofh 00fh...

Page 304: ...F OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF OF 00fh 00fh Oofh Oofh 00fh Oofh 00fh 00fh Oofh Oofh Oofh Oofh Oofh O...

Page 305: ...b db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db oofh 00fh oofh oofh 00fh 00fh oofh oofh oofh OOfh Oofh oofh oofh o...

Page 306: ...db db db db db db db db db db db db db db 00fh 00fh OOfh 00fh Oofh 00fh 00fh 00fh oofh Oofh oofh OOfh Oofh Oofh Oofh oofh Oofh Oofh Oofh oofh oofh Oofh 00fh 00fh 00fh Oofh 00fh Oofh oofh oofh Oofh OO...

Page 307: ...db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db Oofh 00fh 00fh 00i h 00fh 00fh 00fh 00fh Oofh 00fh Oofh oofh 00fh O...

Page 308: ...db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db db end se16821 se16821 se16821 se16821 se16845 se16845 lightpen Oofh Oofh Oofh Oof...

Page 309: ...page 4 99 SEMICONDUCTOR IDENTIFICATION VIOSEL video i o select prom Macr os Symbols LIGHTP 000 3 SEL6 8 2 00 05 SEL684 0006 No Fata l er r o r s...

Page 310: ...OA OB OC OD OE OF db db db db db db db db db db db db db db db db 00 01 02 03 04 Ap A1 A2 05 06 07 08 09 A3 A4 A5 00 01 02 03 04 Ap A1 A2 05 06 07 08 09 A3 A4 A5 10 10 11 12 13 14 15 16 17 18 19 1A 1...

Page 311: ...39 3A 3B 3C 3 0 I 3E 3F db db db db db db db db db b db db db db db db 1E 1F 20 21 22 B2 B3 B4 23 24 25 26 27 B5 B6 B7 1E 1F 20 21 22 B2 B3 B4 23 24 25 26 27 B5 B6 B7 40 40 41 42 43 I 44 45 I 46 47 I...

Page 312: ...1 62 63 64 65 66 67 68 69 I 6A 6B 6C 60 6Er 6F db db db db db db db db db db db db db db db db 3C 3D 3E 3F 40 C4 C5 C6 41 42 43 44 45 C7 C8 C9 3C 3D 3E 3F 40 C4 C5 c6 41 42 43 44 45 C7 C8 C9 70 70r 71...

Page 313: ...59 D3 D4 D5 90 90 1 91 92 93 94 1 95 96r 97 f 98 99 9A 9B 9C 9D 9E 9F 5A 5B 5C 5D 5E D6 D7 D8 5F 60 61 62 63 D9 DA DB db db db db db db db db db db db db db db db db 5A 5B 5C 5D 5E D6 D7 D8 5F 60 61 6...

Page 314: ...3 74 75 76 77 E5 E6 E7 CO CO Cf C2 C3 C4 C5 C6 C7 1 C8 C9 1 CA CB CC CD CE CF db db db db db db db db db db db db db db db db 78 79 7A 7B 7C E8 E9 EA 7D 7E 7F 80 81 EB EC ED 78 79 7A 7B 7C E8 E9 EA 7D...

Page 315: ...91 92 93 94 95 F7 F8 F9 db db db db db db db db db db db db db db db db 8C 8D 8F 90 F4 F5 F6 91 92 93 94 95 F7 F8 F9 FO FO F1 F2 F3 l F4 F5 1 F6 F7 F8 F9 FA FB FC FD FE FF 96 97 98 99 9A FA FB FC 9B...

Page 316: ...nt part A Fi nd the circuit component number R303 C304 etc on the X Ray View B I o cate the same number in the Circuit Component Number column of the Replacement Parts List C Ad jacent to the circuit...

Page 317: ...p T I b b b b b b b off 0 iR 81 1 i U38 1 C l b b U3 8 V322 b b 38 IT M PPED RGB 82 i c I i f 4 86 b b 14 bb o bb bb b b b b b ebb b bbb q b b b 48 42 b i 39 4I VIDEO LOGIC CIRCUIT BOARD Shown from th...

Page 318: ...16 0 00 s O 1 6 0 C l 0 0 0 1 16 1 6 0 EY 3 O 1 6 f Cl Cl 37 38 Y 2 O 1 1 0 0 OO i0 Y 0 0 0 0 324 P3 14 I 4 0 0 000 0 tI O 00 0 0 0 0 48 42 39 41 1 0 0 0 0 0 0 379 GIC CIRCUIT BOARD m the componentsi...

Page 319: ...ata output lines Buffered memory write signal Control signal that requests data on the data input bus Enable clock signal for the 6845 and the 6821 Provides common ground for the system Green video RA...

Page 320: ...tatus signal Write control signal Some other important video signals are BDOTA BLUDO BLUD7 Bl u e data output bus from video RAM Blue dot pixel data signals BLUE CAS BSEL Blue video signal Blue video...

Page 321: ...ignals RED REDDO REDD7 R ed data output bus from video RAM RSEL VERT VAO VA7 VIDRAMSEL Red video RAM select signal VRAM address lines Vertical sync signal Video RAM select signal Indicates CPU has acc...

Page 322: ......

Page 323: ...Page 5 I Video Deflection Board 52 Circuit Description Troubleshooting 5 4 Recalibration Replacement Parts List Circuit Board X Ray Views 5 8 5 5 511 Inside Envelope at rear of manual Schematic...

Page 324: ...acts as the inverting input and its emit ter as the noninverting input The output of the amplifier feeds back to its emitter to ensure good linearity and the RC network between R312 and R317 set the...

Page 325: ...tal circuits 12 volts and the video amplifier 70 volts Video Amplifier The video amplifier is a cascode amplifier consisting of Q401 and Q402 This circuit has high gain low noise and low input and out...

Page 326: ...he Circuit Board X Ray Views for the physical loca tion of parts on the circuit boards CONDITION No high voltage 1 2 3 4 POSSISLECAUSE Q102 Q103 or associated circuitry Connector not plugged into vert...

Page 327: ...RN 3 WA R NING HI GH VOLTAGE I M LECT ION YOKE kl ROAM MAGNET CENTERING T ROT ATE I j I iL PICTORIAL 5 1 Calibration Control Locat...

Page 328: ...WARNING H I GH VOLTAGE W I DTH COIL O Oo FOCLIS Qo BR IT E Qo Oo VERT SIZEQo VIDEO DEFLECT ION BOARD PICTORIAL 5 1 bration Control Locations...

Page 329: ...on the back of the CRT and on the video deflection circuit board As you make adjust ments to these areas use insulated or non metallic tools Adjust the BRITE control clockwise until you see the back g...

Page 330: ...sen the indicated screw and rotate the deflec tion yoke until the edges of the display are vertical and hori zontal Then retighten the screw Adjust the centering rings on the deflection yoke to the po...

Page 331: ...ke at the position which is closest to this location until the display edge is as straight as possible Repeat these adjustments as necessary all around the yoke at any of the eight locations which req...

Page 332: ...6 750 12 6 332 12 6 391 12 1000 Q 1000 Q 22 kQ 1000 Q 4700 Q 2 10 kQ 1 2 watt 2 1000 Q 22 Q failsafe 10 Q 1 2 watt failsafe 180 Q 82Q 100 Q failsafe 680 Q 15 kQ 10 kQ 10 kQ 10 100 kQ control 2200 Q 1...

Page 333: ...C118 C119 C121 C122 C123 C124 C126 C127 C128 C129 C301 C302 C303 C304 C307 C308 C309 C311 C312 C313 C314 C316 C317 C401 C402 C403 234 285 27 161 27 105 25 928 27 161 27 128 27 27 234 284 27 128 21 43...

Page 334: ...CR112 CR301 CR302 CR303 CR304 CR401 Transistors Q102 Q103 Q104 Q301 Q302 Q303 Q304 Q306 Q307 Q308 Q401 Q402 234 270 234 276 234 275 234 275 234 274 234 274 234 270 234 272 234 271 234 270 234 273 234...

Page 335: ...nt part A Fi nd the circuit component number R303 C304 etc on the X Ray View B Lo cate the same number in the Circuit Component Number column of the Replacement Parts List C Ad jacent to the circuit c...

Page 336: ...A w wtlAk Wm4c 4 XW g eagan X333 ClP R401 C118 I BLK C317 g B I 1 ORG 2 Rl ik P Wk 1 4 I g g 4 wms Q G f CX117 2 t l I 61D2 i RN S R189 0 R3qp Qg8 C ea 0302 3 t o VIDEO DEFLECTION BOARD KIT VERSION...

Page 337: ...HORIZ Rqqy P VERI CR O R Oe eaoa c o a k I Oj g N CX 9 N a O3 CII9 s p R313 u 4 30 S c3or e3og R125y glol I LiN C O IL f I H SE g RI4 Vf W I os g 0 IL R 108 1 9 9 N 4IlI l li li m VIDEO DEFLECTION BO...

Page 338: ...ry of Operation Detailed Circuit Description Troubleshooting Calibration Replacement Parts List Semiconductor Identification Circuit Board X Ray View Interconnect Pin and Signal Definitions Schematic...

Page 339: ...8 drives may be used Current software supports only two drives of each type Single or double density single or double sided formats Clock rates up to 5 MHz Stepping rates from 3 to 30 ms Independentl...

Page 340: ...Disk Controller with a CPU that operates faster than 3 MHz no changes are required The Card is ready for operation If you will be using the Disk Controller with a CPU that operates a 3 MHz or slower...

Page 341: ...ough 7 The center row of holes are connected to the S 100 interrupt lines VIO through VI7 which corresponds to the 0 through 7 numbering of the IRQ holes Connect the selected option to the proper cent...

Page 342: ...and 1 are used to control bits 3 and 4 with 0 least significant bit of the status port which can be read at I O address BASE 5 Zenith software currently uses switch section 0 for 48 96 tpi drive selec...

Page 343: ...R OPTIONS Other Options Other jumpers may be required if you change to different type disk drives and recalibration ever becomes necessary See the Calibration section of this Manual for the use of tho...

Page 344: ...I O Port Assignments The following chart lists the I O Port Addresses of the Floppy Disk Controller Card while the DIP Switch Definitions chart in Pictorial 6 4 on Page 6 8 shows how to set the base...

Page 345: ...C Q3 rv o DS1 Undefined Pictorial 6 4 DIP Switch Definitions Port Bit Definitions The definitions of the individual bits written to the 1797 ports listed above are given in the 1797 data sheet in the...

Page 346: ...bits 0 1 and 2 DSEN PRECOMP 5 25 DDEN 0 Precomp on 1 Precomp off 0 Precomp all tracks 1 Precomp tracks 8 DDEN 44 76 Note Precompensation is disabled in single density 0 1797 operates as specified by b...

Page 347: ...not active running 1 Delay active Not defined Set by section 0 of DIP switch on Floppy Disk Controller Card Set by section 1 of DIP switch on Floppy Disk Controller Card DON T CARE Not defined DON T...

Page 348: ...OMP 1 JO X PRECOMP 1 JO X PRECOMP 0 JO X N A 5 25 48 tpi Double Density 5 25 96 tpi Double Density PRECOMP 1 JO INSTALLED PRECOMP 0 JO X PRECOMP 1 JO OUT NOTE PRECOMP is bit 4 of the control latch X i...

Page 349: ...single density in compliance with the IBM double density format Zenith software conventions currently use the Card s DIP switch section 0 status port bit 3 to specify 5 25 drive s track density 0 48 t...

Page 350: ...ve select 3 GND Index sector GND Drive select 0 GND Drive select 1 GND Drive select 2 GND Motor on GND Direction select GND Step GND Composite write data GND Write gate GND Track 0 GND Write protected...

Page 351: ...nge NC In use control GND Two sided GND GND Side one select GND 26 Drive select 0 27 GND 28 Drive s e lect 1 29 GND 30 Drives e lect 2 31 GND 32 Drives elect 3 33 GND 34 Direct ion select 35 GND 36 St...

Page 352: ...sOUT slNP NC sMEMR NC sHLTA NC Clock GND 8 volts NC 16 volts NC Slave CLR NC DMAO NC DMA1 NC DMA2 NC sXTRQ NC A19 NC SIXTN NC A20 NC A21 NC A22 NC A23 NC NDEF NC NDEF NC PHANTOM NC MWRT DO1 Data Out...

Page 353: ...97 COMMAND PORT 1797 STATUS PORT 1797 TRACK REGISTER 1797 SECTOR REGISTER 1797 DATA REGISTER OUTPUT ONLY CONTROL PORT INPUT ONLY AUX STATUS PORT 0003 0004 0008 0010 BIT DEFINITIONS FOR FDCON CONDS EQU...

Page 354: ...Dp p 50 100 0 0 0 4 e C3 4 4 0 Ph Ir COMPONENT BOTTOM S IDE SIDE 0 cs 0 lJ JJ JJ 0 OX g gi l 4 S100 BUS CONNECTION...

Page 355: ...I N STATUS PORT T E R F A C E CONTROL LATCH 5 25 1797 DATA AND WR ITE PRECOMPEN SATION SEPARATION BLOCK DIAGRAM...

Page 356: ...IDE ZERO USING IBM COMPATIBLE SECTOR LENGTH FIELDS VARIOUS BITS IN THE READ COMMAND ALTER THESE PARAMETERS SEE THE 1797 DATA SHEETS IN TYPICAL APPLICATIONS IT WILL BE NECESSARY TO COMPUTE THE READ COM...

Page 357: ...GENERATED UNTIL DRQ PLACE IN MEMORY INCREMENT POINTER DECREMENT BYTE COUNT TEST FOR COUNT O CONTINUE TO END OF SECTOR READ AUX STATUS WAIT FOR IRQ NO IRQ YET READ STATUS SAVE STATUS WAIT FOR NOT BUSY...

Page 358: ...INCREMENT POINTER DCX DECREMENT BYTE COUNT MOV TEST FOR COUNT O ORA JNZ WLOOP1 IN ANI JZ WLOOP2 IN MOV ANI JNZ MOV IN NOTE THAT FORMATTING A TRACK IS ACCOMPLISHED BY USING THE WRITE TRACK COMMAND INS...

Page 359: ...INCLUDING THE TRACK TO TRACK SEEK TIMING AND MAY HAVE TO BE ALTERED IN SPECIFIC APPLICATIONS IT SHOULD BE NOTED THAT SOME DR I VES MAY SCRIBBLE ON DISKETTES WI TH UNDESIRABLE RESULTS UNLESS THE SOFTWA...

Page 360: ...write precompensation circuitry and the two drive interfaces Bus Interface The bus interface meets the proposed IEEE 696 standard for an S 100 bus The bus interface is made up of a connector two octal...

Page 361: ...r The 1797 controls the placement of information on the disk ette That is the movement of the drive head the formation of written data and the separation of the read data is con trolled by the 1797 Da...

Page 362: ...hese pins are used in read operations from the status latch or from the 1797 controller The data is buffered from the Card s internal data bus to the S 100 bus by means of U36 a 74LS244 buffer Data Ou...

Page 363: ...s are buffered by U33 Vector Interrupt Lines The vector interrupt lines from the bus leave the Card through pins 4 through 11 of the bus interface They may be driven by U32 Ready Line The ready line R...

Page 364: ...kept high by Q2 and Q3 until the supply voltage is at or above 4 volts at R25 When the supply reaches 4 volts Q2 and Q3 are biased near their operating region and will conduct when WG is made active...

Page 365: ...is also present the simultaneous assertion of EOUT and I O signals are passed to U20B a flip flop whose Q and Q outputs are as serted when the Address Latch Enable ALE signal clocks its pins 3 and 11...

Page 366: ...ignals are ANDed by U21 gate B When both YO and pWR are active gate B produces an active low clock whose trailing edge activates U30 The control latch receives the control byte from the internal data...

Page 367: ...pWR After the proper control words are sent to select the power drive address lines AO and A1 are made high and A2 is made low connecting the data register of the 1797 to the internal data bus As long...

Page 368: ...signal presets flip flop U26 part A Flip flop U26 qualifies the FDSEL signal to enable read write operations in anticipation of the RDY line being made active From D3 of U19 the DRQ signal is output t...

Page 369: ...oppy Disk Controller Card can generate the interrupt request INTRQ and the data re quest DRQ Both of these interrupts originate from the 1797 The INTRQ signal is sent to indicate a command completion...

Page 370: ...verted by U6 NAND gate B while the TWOSIDED signal is inverted by U6 NAND gate D 5 25 Drive Interface The 5 25 drive interface connects to the drive cable through the P2 All output signals to the driv...

Page 371: ...ard seated properly in the socket If the answer to all of the above questions is yes and the Card still does not work properly then you should call Yo ur local Zenith Data Systems Dealer OI Th e n ear...

Page 372: ...re DIP switch on Disk Controller is set at the correct address Check positions of P1 and P2 on the Disk Controller Be sure drive 1 is jumpered for drive 1 selection Verify a properly configured and co...

Page 373: ...digit readout A 10 MHz bandwidth calibrated laboratory quality oscil loscope with a sweep speed of 50 ns division and a verti cal deflection of 2 V division and a low capacitance X10 probe A f r eque...

Page 374: ...G ND CP2 CP3 R 3 R 4 o Ij QQQQQQQQQ Q Q Q Q Q Q Q Q Q XXQXXQQXQ Q Q amzm PICTORIAL 6 5 Caiibration Locations...

Page 375: ...the manufacturers of the drives should supply this information with their product If the value of precompensation is higher for the 5 25 drives or if you only have 5 25 drives go to Step 9 If the val...

Page 376: ...diskette in any of the 5 25 drives by running the FORMAT program provided on your operating system diskette 12 Wh ile FORMAT is running turn R3 to adjust the pulse width displayed on the oscilloscope...

Page 377: ...V 5 Rem ove the voltmeter test leads 6 Set the six digit frequency counter to count 4 MHz 7 Atta c h the shield lead to GND and the signal lead to CP1 8 Adj ust R1 shown in Pictorial 6 5 for a reading...

Page 378: ...R23 R24 R24A R24B R25 R26 47kD 1o C4 C6 C7 C8 C9 C25 C26 C27 C28 C29 C30 C31 C34 C35 C36 C37 C38 C39 C40 C47 C48 C49 C50 C63 1 MO 1000 Y 3900 tt 1800 tt 47kt 1 7200 1 25 kO 1 120 kD 2370 1 1 Mtt 3900...

Page 379: ...ponent Number Index This index shows the Part Number of each semiconductor CIRCUIT COMPONENT NUMBER HEATH PART NUMBER HEATH PART NUMBER CIRCUIT COMPONENT NUMBER D1 D3 Q1 Q2 Q3 U1 U2 U3 U4 U5 U6 U7 U8...

Page 380: ...number Diodes HEATH PART NUMBER MAY BE REPLACED WITH DESCRIPTION LEAD CONFIGURATION TOP VIEW INDORIANT TNI IANDFO FNOOf DIODFSCAN li NARN D IN A NON F R OfWATS 1N4148 1mA75V SILICON Transistors HEATH...

Page 381: ...H DESCRIPTION LEAD CONFIGURATION TOP VIEW 442 54 UA 7805 5 V REGULATOR OR 442 663 LM 78M12 12 V REGULATOR IN COAI CONI OUT OU1 VIN VOU7 442 708 ADJUSTABLE REGULATOR V IN I ADJ 6A 6Y 5A 5Y 4A 4Y 141 13...

Page 382: ...74LS74 DUAL D FLIP FLOPS 0 CLR 0 CK PR 0 IPB D CLR 0 CK PR 0 I 2 3 4 5 6 7 I CLR I D I CK I PR I Q I 0 G IVD VI 0 40 40 4D 3D 3Q 3Q CLQCK 1 5 1 4 13 1 2 11 1 0 9 0 Q 0 CK CLR 0 Q CLR 443 752 74LS175 Q...

Page 383: ...Vcr 2G IYI 2A4 IY2 2A3 IY3 2 A2 IY 4 2AI 1 9 18 1 7 1 6 15 1 4 1 3 1 2 11 I H G F 443 791 74LS244 TRI STATE BUFFER DRIVERS C D A B 7 8 9 1 0 2 A4 IA 2 2 Y 3 IA3 2Y2 IA4 2YI G ND I 2 10 I AI Ycc 48 4A...

Page 384: ...1 443 805 74LS273 Q D CK CLEAR D 0 CK CLEAR 0 0 CK CLEAR D Q CK CLEAR OCTAL D FLIP FLOPS CLEAR CLEAR C LE AR CLEAR C K CK CK CK 0 D D 0 D D 0 1 2 3 CLEAR 10 1D 4 5 6 7 8 9 10 2D 2Q 3 Q 3D 4D 4Q GND V...

Page 385: ...T 10 CONTR OI 3 II 5 6 2 8 9 10 1 D ZD 2 Q 3 Q 3D 4D 4 Q G ND V 48 4A 4Y 38 3 A 3Y 1 4 13 1 2 l l 1 0 D 443 875 74LS32 QUAD 2 INPUT OR B A Ii 1 IA 18 1 Y 2 A 28 2Y GND DATA OUTPUTS Vc YD 16 Yl YZ Y3 Y...

Page 386: ...1 8 1 7 1 6 15 1 4 1 3 1 2 1 1 443 971 74LS688 8 BIT COMPARATOR 1 2 3 4 5 7 8 9 1 0 G PO OO P l 0 1 i OZ 3 03 G i 90 C3 Ci V 40 39 38 37 36 35 34 33 3 2 31 30 29 Z8 27 26 25 24 23 22 21 1797 FLOPPY DI...

Page 387: ...4 VOLTAGE CONTROLLED OSCILLATOR FREQ CO i NTROL 1 RANGEC Y EXT EN 3 4 5 A 7 G ND RANGE CXI CX 2 E NABLE Y G ND OUTPUT OSC STP 84PW 83PliV 82PLV 81PW OUT STB IN OUT 16 15 14 13 12 11 10 C C I P W 18 17...

Page 388: ...NUMBER MAY BE REPLACED WITH DESCRIPTION LEAD CONFIGURATION TOP YIEW RX2 CD2 14 1 3 II 0 02 Q2 1 2 11 0 CX2 16 1 3 443 1040 S6LS02 MULTIVIBRATQR 4 3 6 7 I 1 0 QI 0I Gl D I 2 3 CXI lXI CDI CC 4Y 48 4A...

Page 389: ...ment part A Find the circuit component number R13 R14 etc on the X Ray View B Locate this same number in the Circuit Component Number column of the Replacement Parts List C Adjacent to the circuit com...

Page 390: ...R9 1 R4 Ri R1 TG43 PS U1 R 19 U18 U21 I Z 14 UaS U32 CIRCUIT I Shown from the c component...

Page 391: ...14 BE E It 24 24B D 2 D3 R25 U22 RP 1 28888 CIRCUIT BOARD X RAY VIEW from the component side The foil on the omponent side is shown in red...

Page 392: ...ernal data bus Double density enable Data in bits on the S 100 bus in with respect to the CPU not the controller Direction of drive head When high the drive head is stepping in When low the drive head...

Page 393: ...aster reset pin on the 1797 Controller chip that sets all registers in the chip to a known state Data request on data in bus pDBIN pSTVAL pSYNC PU PD pWR PRECOMP RAW READ Satus valid New bus cycle may...

Page 394: ...output When high side 1 is selected in the drive When low side 0 is selected Status signal signifying data input to the bus read cycle may occur Status signal signifying data output from the bus writ...

Page 395: ...Wait enable Set the RDY line low on all accesses of the 1797 data register Write data Contains the data to be written onto the diskettes as well as the clock sig nals Write data into the 1691 phase lo...

Page 396: ...a pulses that have been reshaped by U16 5DSO 5DS3 Five inch drive select signals 5 FASTSTEP Enables fast stepping in the 5 25 drives 8 5 CLOCK 8DSO 8DS3 Selects between the 8 and the 5 25 drives Eight...

Page 397: ...Page 7 1 5 1 4 Floppy Drives 7 2 Description Programming Cable Connections Operation 7 5 7 6...

Page 398: ...ad Write gap type heads The head carriage is positioned by a stepper motor that moves the head carriage in 02083 steps producing 48 tracks per inch TPI The disk controller card in your Computer is the...

Page 399: ...1 1 1 1 Ii 1 1 1 1 1 1 1 PR OG RAIrl IVIING I II 4 32 T 168 I P L LIG HARDWARE UNIT ONE INSET TE Rhl I NAT0 R NET QRK Oa I tt tf t1 Il tIIL II WilfrI I C CCCCCCCCCcCSiCC CCS 1 1 1 1 1 1 1 I 1 I 1 1 1...

Page 400: ...7 1 However each Computer system no matter how many 5 1 4 floppy drives it has should have only one drive with a terminator IC installed in it This terminator IC should be lo cated in the drive that...

Page 401: ...e 7 5 CABLE CONNECTIONS Refer to Pictorial 7 3 for a view of cable connections FLOPPY DR IVE UN IT POWER PLUG D L4yy L L L L L L L L L SMALL TRIANGLE MARKED EDGE OR Pictorial 7 3 Connecting Drive Cabl...

Page 402: ...e e p the diskette away from magnetic fields Magnetic fields can distort the recorded data on the diskette 3 Replace damaged or worn st orage envelopes 4 Write on the plastic jacket only with a felt t...

Page 403: ...ite protected so that it cannot be written on To do this cover the side notch with a tab or opaque tape See Pictorial 7 5 READ WRITE ACCESS SLOT WR ITE ENABLE NOTCH TAB OR OPAQUE TA PE 3 a o Al X I WR...

Page 404: ......

Page 405: ...Page 8 1 Power Supply Power Line Considerations Specifications 8 2 8 3...

Page 406: ...opera on Also read and comply with the following information The plug on the power cord is for standard 115 VAC outlets For 230 VAC operation in the U S A replace the line cord and connector in a man...

Page 407: ...shuts down power supply 5 VDC 3 at 12 amperes maximum Including ripple 2 amperes minimum Ripple 100 mV peak to peak maximum 12 VDC 5 at 5 2 amperes maximum with 5 VDC load at 6 amperes Including rippl...

Page 408: ...res maximum Ripple 50 mV peak to peak maximum All In One Version Only Zenith Data Systems reserves the right to discontinue products and to change specifications at any time without incurring any obli...

Page 409: ...Page 9 1 Chassis Cabinet Cables 9 2 Replacement Parts List Cables Location Description 9 12 Circuit Boards 8 Hardware 9 17...

Page 410: ...e or All ln One All In One Model The following Key Numbers correspond to the numbers on the All in One parts pictorials ns indicates a part that is not shown KEY PART NO NO DESCRIPTION 1 2 3 4 5 6 7 8...

Page 411: ...page 9 3 REPLACEMENT PARTS LIST V s 1 s I t V p 10 ALL IN ONE...

Page 412: ...ns 34 conductor cable disk drive to disk controller board Drive chassis mounting plate 6 32 x 3 8 hex head screw Disk drive 5 1 4 48 tpi Drive panel 0 6 x 1 4 phillips head screw Dual drive escutcheo...

Page 413: ...92 763 234 292 234 268 Grommet CRT support bracket 6 32 x 3 8 hex head screw 10 x 1 1 2 hex head screw 10 flat washer CRT 12 green phosphor CRT 12 white phosphor CRT 12 amber phosphor Yoke CRT support...

Page 414: ...60 61 ns 234 256 S 100 card cage S 100 card rack Back panel 4 lockwasher Large 4 40 nut Floppy cable 8 drive 50 conductor Cable RGB out Control 500 0 1 4 lockwasher 6 x 1 4 sheet metal screws 1 4 x 3...

Page 415: ...Page 9 7 ACE5fENT p4RTS L 45 44 43 46 61 42 60 40 50 52 I...

Page 416: ...58 750 206 1456 150 142 262 56 250 512 92 760 203 2125 203 2124 234 200 234 257 Top cover Slide rail Spring Drive shield Disk drive 5 1 4 48 tpi Threaded pin tfr8 x 3 4 self tapping screw Drive shelf...

Page 417: ...page 9 9 REPLACEMENT PARTS LIST 1 4 9 io 20 1II l I i jj e e 1 I 17...

Page 418: ...254 9 94 631 206 1416 200 1418 1 7 conductor video RGB cable 50 conductor flat cable Large 4 40 nut P4 lockwasher Card rack Card cage Chassis Nut P6 washer Back panel 4r6 x 1 4 sheet metal screw 1i4 l...

Page 419: ...Page 9 f E LACEMENT pRTS LIST 23 24 h 2S 26 28 29 L 41 40 C 3 0 I t tj t 3 4 Q t...

Page 420: ...P305 on the video logic board to P104 and P106 on the main board 134 1257 134 1246 134 1254 134 1265 34 conductor flat cable From J1 of each disk drive to P2 on the disk controller board 7 wire cable...

Page 421: ...f c 6 c FOR Ij INC HESTER DR IVE E Pictorial 9 1 Power Supply Cables B 8 wire socket blk wht blu blu blu yel blk to main board plug P101 8 wire socket blk blk red red red blk blk to main board plug P...

Page 422: ...c Board MARKED VIDEO LOGIC CIRCUIT BOARD EDGE I l Pictorial 9 2 Video Logic Cables 40 conductor cable from plug P104 to the main board plug P304 Part number 134 1257 40 conductor cable from plug P106...

Page 423: ...15 CABLES LOCATION DESCRIPTION Keyboard X I AI A IN If I KEYBOARD v v Pictorial 9 3 Keyboard Cables 20 conductor flex cable to the main board plug P105 10 conductor flex cable to the main board plug...

Page 424: ...K TO HORIZONTAL YOKE To VERTICAL YOKE VERT YOKE Pictorial 9 4 Video Deflection Cables 6 wire socket from the power supply and video board to the 10 pin plug on the video deflection board 2 wire socket...

Page 425: ...1411 250 1413 254 9 252 15 252 2 4 40 x 1 4 screw 4 40 x 1 2 screw 4 lockwasher Small 4 40 nut Large 4 40 nut 6 Hardware 250 1422 250 1307 250 1325 250 1264 250 1199 254 6 254 1 252 3 6 32 x 1 4 flat...

Page 426: ......

Page 427: ...General Information Devices Permitting User Programming Port Addresses Z DOS Initialization Sequence ASCII Chart Escape Codes Escape Codes Defined Key Code Chart Keypad Code Chart Function Key Code Ch...

Page 428: ...ION This section of the Manual provides condensed system pro gramming information It is provided for the experienced pro grammer to help him understand the Computer System so he can develop his own so...

Page 429: ...function Reset 8088 Key Facts Clock Speed Address Space Interrupts DMA 5 MHz 20 bits extended to 24 NMI NMI or power failure TEST jumperable to 0 or 1 Vectored by 8259 External devices and p rocessor...

Page 430: ...nal Device Type Number LEVELS 0 Highest MASTER Error Parity error or S 100 pin 98 Processor swap interrupt Timer 8253 Out 0 or Out 2 Slave 8259 Serial port A Serial port B Keyboard or display Printer...

Page 431: ...Interrupt generation is enabled by writing a 1 to bit 1 of the PSP If interrupts are not masked the currently selected processor is signalled when an interrupt is requested If the MASK mode is select...

Page 432: ...shows which port bits control the fourROM configurations 3 2 BITS DEFIN ITION 00 Option 0 10 Option 2 01 Option1 11 Option3 Option 0 the power up or master reset configuration makes the code in ROM a...

Page 433: ...he RAM block from 0 to 48K with the block at 64 to 112K Option 2 swaps the RAM block from 0 to 48K with the block at 112 to 160K Option 3 swaps the RAM block from 4 to 60K with the block at 68 to 124K...

Page 434: ...2 are tied to a 250 kHz 4 p s clock and the CLK1 nput is tied to the output of channel 0 The two outputs that are available externally are OUTO and OUT2 These are ORed together to produce the timer in...

Page 435: ...h the 8253 device BIT DEFIN ITION 0 0 Use 16 bit binary counter 1 Use 4 decade binary coded decimal counter 1 000 Mode0 2 X 10 Mode2 3 100 Mode4 4 00 Counter latch cant byte 001 Mode1 X11 Mode3 101 Mo...

Page 436: ...tion for pro gramming information These IC s include 8259 s 6845 2661 s Interrupt controllers CRT controller CRT C Synchronous asynchronous data communica tions controller Parallel interface controlle...

Page 437: ...Serial A Printer Port 8253 Timer Parallel Port Main Board reserved by ZDS Light Pen Control OF6 OFA OF4 OF5 OF2 OF3 OFO OF1 OEC OEF OE8 OEB OE4 OE7 OEO OE3 ODF ODE 6845 CRT Controller Video 68A21 Par...

Page 438: ...imal Device MTR 100 Monitor ROM Firmware reserved by ZDS Network Card NET 100 Video RAM Green Plane Video RAM Red Plane Video RAM Blue Plane User RAM ET 100 Reserved Addresses in addition to those lis...

Page 439: ...will chip select the PIA by assert ing the 6821CS control line from the I O port decoder The CPU asserts the OUT line pin 21 when the Computer needs to write to the PIA In all other cases the PIA will...

Page 440: ...ughly discuss each of these func tions The Loader The purpose of the loader is to load in lO SYS and pass con trol to it The first 512 bytes of every diskette or full sector if sector sizes are greate...

Page 441: ...m 4 sectors to 17 sectors depending on the disk format This allows the loader to be smaller since it does not have to read in the directory See Pictorial 10 2 TOP OFSYSTENI MEMORY LOADERCODE 0 400 1K...

Page 442: ...and insures that the first named file is IO SYS It also determines if the diskette drive should be double stepped which is necessary if 48 tpi media is used in a 96 tpi drive Once IO SYS is located it...

Page 443: ...ata Bytes sector Once IO SYS has been read intomemory at address 40 0 see Pictorial 10 4 the loader executes a far jump to IO SYS and the source index Sl register points to the diskette para meter tab...

Page 444: ...Parameter Table Byte 0 2 22 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Bit 0 1 2 3 Bit 0 1 2 3 4 5 6 7 Near JMP Version number should be 1 Sector size in bytes Sectors per cluster Number of re...

Page 445: ...are set into the interrupt page 3 The interrupt routine addresses for the timer slave 8259A serial ports A and B keyboard display light pen parallel port and the eight slave interrupt lines from the...

Page 446: ...are enabled The configuration information setup by CONFIGUR is now used to initialize the Z DOS devices PRN AUX and CON The defaults for these devices are PRN Serial A 4800 baud DCD high AUX Serial B...

Page 447: ...ds no existing drive it marks the imaginary drive as real and sets the flag to indicate that the system should not allocate any imaginary drives to this drive This is done for the user who forgets to...

Page 448: ...le Z DOS SYS is read into memory the DOS INIT routine in Z DOS SYS is called with pointers to the disk parameter table and a flag tells Z DOS to size memory See Pictorial 10 5 TO OFAIEMORY SYSTEM ROM...

Page 449: ...der checks for AUTOEXEC BAT gets the date and time from the user and prints the system prompt Then the operating system is fully in control and the user is ready to begin executing programs See Pictor...

Page 450: ...Z DOS INITIALIZATION SEQUENCE Sample Programs NOTE Label definitions for the following programs can be found in the Z DOS Distribution Disk II definitions files or in Appendix I of Volume II of the Z...

Page 451: ...OUT IN IN AL AL Turn off unit ZSERA EPCMD AL AL ZSERA EPCMD Reset mode reg p t r A L EPSB1 EPCL8 EPA16X Set mode reg 1 ZSERA EPMODE AL AL EPMR2A EPB960 Set mode reg 2 ZSERA EPMODE AL AL EPNORM EPRTS E...

Page 452: ...e CA2 to be set and cause interrupts MOV AL P IADDAC PIAC12 PIAC23 Set control port A for data OUT ZPI A P I ACTLA AL Disable tr ansitions of parallel printer to cause interrupt MOV AL PI A DDAC Set c...

Page 453: ...AL Timer 1 XOR OUT OUT MOV OUT MOV OUT Wait for first rising clock from counter 0 MOV OUT XOR TIMEL IN TEST LOOPZ JNZ JMP AL OFFH ZTIMERSO ZTIMERS AL CX CX Get timeout value AL ZTIMERS AL ZTIMERSO TIM...

Page 454: ...selves Get segment Point to next segment finished N o tr y a g a i n R estore seg r e g s MOV MOV MOV MEMIF Initialize the Slave 8259A interrupt controller MOV OUT MOV OUT MOV OUT MOV OUT AL ICW10P IC...

Page 455: ...AL Slave is connected to line 3 AL ICW4UPM ICW4SFN ZM8259A ICW4 AL Set processor to 8088 special fully nested nonbuf fered AL NOT OCW1IMO OR OCW1IM2 OR OCW1IM4 OR OCW1IM5 OR OCW1IM6 ZM8259A OCW1 AL Al...

Page 456: ...L G H R S 0 P Q X T U V W CTRL DESCRIPTION Null tape feed Start of Heading Start of text End of text End of transmission Enquiry Acknowledge Rings Bell Backspace also FEB Format Effector Backspace Hor...

Page 457: ...2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C I I II II I I 0 1 0 1 23 4 5 6 7 8 23 4 5 6 7 8 9 EM SUB ESC ESC FS GS RS US SP Y Z A End of medium Substitute Escape File separator Group separat...

Page 458: ...7 58 59 5A 5B 5C SD Z S CHAR A B A B G H I G H I C D E F C D E F J K L M N J K L M N 0 P 0 P Q R Q R T U T U V W X Y V W X Y S KEY CTRL DESCRIPTION Equal sign Greater than Question mark At sign Letter...

Page 459: ...ltllltl I I I I l l I l l l l 137 9 5 5F l i t I Il II II Grave accent 140 9 6 60 I Il Letter a tttilltl 141 9 7 61 a a 142 9 8 62 b b I I I I t i l l I I I tilt Letter b I 143 99 6 3 c c I lilt II ll...

Page 460: ...2 66 I Ill I 147 103 67 g g Letter g ill I il l 150 104 6 8 h h Letter h I I I I I I I I 151 105 6 9 i i I I I I I I I I I I I I I I I Letter i 152 106 6 A j j I 1 1 1 1 1 1 1 1 1 11 1 1 1 1 11 1 I 1...

Page 461: ...6 110 6 E n n Letter o 1111 1111 I Ill I II I 1 11 1 157 11 1 6 F o o Letter p 1111 11 I I I Ill I I I 11111111 IIII 111 11 I I I 160 112 70 p p Letter q 161 113 71 q q j i l l 1111 1111 1111 I I I I...

Page 462: ...4 164 116 74 4l 165 117 7 5 u u Letter u 0 I I I t 1i I Letter v 00 II Ll I 4 I j I t tl il 166 118 7 6 v v l4 iti IO Letter w I 4 l l ll N I I j 4 C I jI 167 119 7 7 w w I 44 t 170 120 7 8 x x Letter...

Page 463: ...llll llllllll ll ll ll 1 74 124 7C Vertical bar broken I I ll 175 125 7D Right brace I I l l l l l l I I 176 126 7 E l l II I I I ll II l l I I I I I Tilde 177 127 7F DE L DE LETE Delete rubout Graphi...

Page 464: ...ly saved position ESC A ESC B ESC C ESC D ESC M ESC I ESC Y ESC j ESC n ESC IR Erasing and Editing ESC E ESC J ESC K ESC L ESC M ESC N ESC 0 ESC ESC b ESC I ESC o Clear display and home cursor Erase t...

Page 465: ...o mode Exit reverse video mode Enter keypad shifted mode Exit keypad shifted mode ESC x Ps Set modes Where Ps equals 1 2 4 5 6 7 Enable 25th line No key click Block cursor Cursor off Keypad shifted En...

Page 466: ...rd auto repeat Disable key expansion Disable event driven key up down mode power up configuration Reset to Additional Functions ESC Z Iden tify as VT52 ESC K ESC Trans mit page ESC Trans mit 25th line...

Page 467: ...lowing sequences but it will not respond to them if they are received by the Computer ESC J ESC S ESC T ESC U ESC V ESC W ESC P ESC Q ESC R ESC OI ESC OJ ESC OK ESC OL Function Key FO Function Key F1...

Page 468: ...ht If the cursor is at the right end of the line it will remain there ESC 0 Cursor Left Moves the cursor one character position to the left back spaces If the cursor is at the start left end of a line...

Page 469: ...I character If the line number entered is too high the cursor will not move If the column number is too high the cursor will move to the end of the line This is the only way to move the cursor to the...

Page 470: ...L Insert Line Inserts a new blank line by moving the line that the cursor is on and all following lines down one line Then the cursor is moved to the beginning of the new blank line ESC M Delete Line...

Page 471: ...shifts to the right As each new char acter is inserted the character at the end of the line is lost ESC b Erase To Beginning Of Display Erases from the start of the screen to the cursor and includes t...

Page 472: ...e Exits the graphics mode and returns to the display of normal characters ESC En ter Alternate Keypad Mode Enters the alternate keypad mode which will then allow the keypad keys to transmit the follow...

Page 473: ...ers the reverse video mode so that characters are dis played as black characters on a white background ESC q Exit Reverse Video Mode Exits the reverse video mode ESC t Enter Keypad Shifted Mode Invert...

Page 474: ...auto CR on receipt of line feed nonblinking cursor disable keyboard auto repeat enable key expansion enable event driven key up down mode ESC y Ps Reset Modes Resetsspecialmodes where Ps equals 1 dis...

Page 475: ...ine Transmits the 25th line The computer requires a special routine to use this feature ESC Tra nsmit Current Line Transmits the line that the cursor is currently located on The computer requires a sp...

Page 476: ...r it was inhibited by an Keyboard Disabled command ESC Keyboard Disable Inhibits the output of the keyboard ESC v Wrap Around At End Of Line The 81st character on a line is automatically placed in the...

Page 477: ...above ESC T Function Key F2 Same as above ESC U Function Key F3 Same as above ESC V Function Key F4 Same as above ESC W Function Key F5 Same as above ESC P Function Key F6 Same as above ESC Q Functio...

Page 478: ...iers such as the A key In the following table an NC under a modifier indicates that no code is generated for that key The CAPS LOCK column has a Y yes or N no to indicate if the CAPS LOCK key affects...

Page 479: ...e Key 35 25 35 25 53 D3 5 5E 36 1E 52 D2 36 37 26 51 D1 26 2A 2A 50 DO 38 39 28 28 5A DA 39 41 01 01 07 87 61 42 02 02 13 93 62 63 43 03 15 95 03 04 05 85 04 65 45 05 OD 8D 05 66 46 06 04 84 06 67 47...

Page 480: ...6E 4E OE 92 OE 6F 4F OF OF 99 19 50 10 10 1A 9A 70 71 51 OF 8F Q 52 12 OC SC 72 53 13 13 06 86 73 54 14 14 OB SB 74 75 15 09 89 55 56 16 16 14 94 76 77 57 OE SE W 58 18 18 16 96 78 59 19 19 OA SA 79...

Page 481: ...ck Yes No Down Code Up Code Key 1B 1B 1B 1B 4F CF ESC 20 20 20 20 45 C5 SPACE 22 27 22 48 C8 27 3C 2C 3C 4D CD 2C 5F 2D 1F 5C DC 2D 3E 2E 3E 4A CA 2E 3F 2F 3F 4B CB 2F 3A 3B 3A 49 C9 3B 2B 3D 2B 5D DD...

Page 482: ...2 DELETE 8D CD 8D CD 38 B8 ENTER HELP D5 95 C5 46 C6 95 96 D6 96 D6 27 A7 FO F1 97 D7 D7 26 A6 97 F2 98 D8 D8 25 A5 98 F3 D9 99 D9 24 A4 99 F4 9A DA DA 23 A3 9A F5 DB 9B DB 22 A2 9B F6 9C DC 9C DC A1...

Page 483: ...ow left arrow A4 A5 Aj A6 A8 E5 E4 E8 E7 E6 A4 A6 A5 A7 A8 E4 E5 E6 E7 E8 38 2F 3A 33 AF 88 BA 83 BF 3F HOME A9 E9 A9 E9 87 37 BREAK keypad keypad 0 keypad 1 keypad 2 keypad 3 keypad 4 keypad 5 keypad...

Page 484: ...wn Code Up Code Key B7 F7 B7 F7 36 B6 7 keypad 8 keypad 9 keypad B8 F8 F9 B8 B9 F8 F9 3E 32 BE B2 B9 FAST REPEAT NC NC NC NC EO 60 CAPS LOCK SHIFT right CTRL SHIFT left RESET NC NC NC NC NC NC NC NC N...

Page 485: ...IFT4 SHIFT5 SHIFT6 SHIFT7 SHIFT8 SHIFT9 0 1 ENTER 0 ESCL ESCB ESCM ESCD ESCH ESCC ESC ESCO ESCA ESCN ENTER 0 ESCL ESCB ESCM ESCD ESCH ESCC ESC ESCO ESCA ESCN ENTER ESC M ESC n ESC m ESC p ESC q ESC r...

Page 486: ...CHR D CHR DEL LINE INS LINE 1 ESC L ESC A ESC B ESC C ESC D ESC H ESC ESC ESC J ESC S ESC T ESC U ESCV ESC W ESC P ESC Q ESC R ESCO I ESCO J ESCOK ESCOL ESC ESCO ESC N ESC M ESC A ESC B ESC C ESC D E...

Page 487: ...splay 4 6 Color output 4 55 Composite 4 56 Configuration 10 48 Contrast control 4 4 CPU read 4 62 CPU write 4 62 CRT C 4 8 CRT C read 4 63 CRT C registered 4 40 Cursor functions 10 42 BDOTA 4 55 Block...

Page 488: ...Address lines 6 24 Assembly language code 6 16 Bus interface 6 21 Calibration 6 35 Card clock speed 6 3 Circuit description 6 23 Control latch 6 22 Control latch bit definitions 6 9 Control lines 6 24...

Page 489: ...tialization sequence 10 14 Interconnect pin definitions Main board 2 137 Keyboard 2 139 Light pen 2 139 Parallel port 2 138 RS 232 2 137 S 100 bus 2 137 Video logic board 2 141 Video logic board 4 109...

Page 490: ...roprocessor 8088 2 28 General 2 28 Pin out description 2 29 Timing 2 32 Microprocessor status code 2 43 Parity circuits 2 59 Processor swap port 2 33 Auto swap 2 37 General 2 33 Swap interrupt 2 38 Sw...

Page 491: ...its main board 2 59 Phantom line 2 52 2 64 4 23 Pixel 4 5 4 40 Polling 3 5 Port addresses 2 6 10 11 Port D8 4 32 Power supply 5 3 Power supply 8 1 Specifications 8 3 Processor swap port FE 2 9 Program...

Page 492: ...Color display 4 6 Contrast control 4 4 Conversion from character based to pixel based display 4 11 Replacement Parts List 4 70 U UPI 8041A 2 75 CRT C 4 12 Description 4 2 Interconnect pin definitions...

Page 493: ...ate 2 44 Wait control 5 6 Width control 2 44 X X Ray views Floppy disk controller board 6 49 Main board 2 136 Video deflection board 5 11 Video logic board 4 106 Z DOS drive mapping 10 21 Z DOS initia...

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