Zenith Z-100 Series, Technical Manual

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Page 2.12
PROGR A M M ING INFORMATION
The following chart shows which port bits control the four ROM
configurations.
BITS DEF I N ITION
3 , 2 0 0
=
Option 0
10
=
Option 2
01
=
Option1
11
=
Option 3
Option 0, the power-up or master reset configuration,
makes the code in ROM appear to be in all of memory
when reads are performed. Writes, however, occur nor-
mally.
Option 1 makes the ROM code appear to be at the top
of every 64K page of memory.
Option 2 makes the ROM code appear to be at the top
of the first megabyte of memory.
Option 3 disables the ROM.
Parity consists of a parity bit for each byte in RAM. This adds
one, two, or three 64K-bit chips (depending on how much
RAM is installed: 64K, 128K, or 192K) and the associated
support circuitry.
RAM parity has two control options: ZERO PARITY and
KILI PARITY. The ZERO PARITY option sets the parity to
the zero state. This sets the parity bit to 0 regardless of the
data pattern that was written and can be used to force a parity
error to check the parity logic. The option is activated by writ-
ing a 0 to bit 4 of the Memory Control Latch (MEMCTL) port.
The KILI PARITY option disables the parity checking circuitry
by writing a 0 to bit 5 of the MEMCTL port. It also clears
a parity error by first writing a 0 to bit 5 and then a 1.