Zenith Z-100 Series, Technical Manual

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Page 4.68
CIRCUIT DESCRIPTION
At the same time, U361 pin 8 goes low to bring VIDRAMRDY
high. The CPU leaves the wait state and finishes processing
the instruction. CRTRAMSEL goes high to drive U379 pin 13
low. Since VIDRAMSEL is also low, U355 pin 3 goes to logic
zero to clear U361.
The CRT-C again has control of the video board.
Light Pen Circuits
T he light pen s t robe e n ters U362 pi n 1 2 f ro m U 1 1 6 pi n 9
( see th e p a r a l lel p o r t d e s c r iption f o r m o r e d e t a i l). T h e
D OTCLK signal toggles L T P N STB t h rough U 36 2 p i n 9 t o
U356 pin 5 . N e xt, th e c l ock s ignal at U 35 6 pi n 1 1 l a tches
the LTPNSTB signal onto U356 pin 9. This positive-going sig-
nal latches the r efresh address into the C R T -C's light pe n
register. See the CRT-C IC data sheets.
Also, the output of U356 pin 5, PENSTBD, goes to U315 pin
11. U315 is an oc tal latch that is loaded by the C RT-C row
address lines, RAO-RA3, and the 4-bit down-counter, U324.
At the time of PENSTBD, RAO-RA3 point to the row that was
active when the light pen strobe occurred; U324 points to the
dot position.
As explained in the parallel port description, when LTPNSTB
asserts, the parallel port sends an interrupt to the CPU. From
here, it is up to the user's program to process the interrupt.
If the CPU is programmed to respond to a light-pen interrupt,
it will read th e d at a s t ored in th e C R T-C l ight-pen register
and the data stored U315 to find the exact pixel location. The
C PU reads the C R T-C a s d e s c ribed earlier; it reads U 3 15
by asserting LTPNCS from the VIOSEL PROM and DBIN from
the S-100 bus. From here, the CPU can compute the video
memory location and access the bit in that memory location
to be processed.