Zenith Z-100 Series, Technical Manual

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Page 2.64
CIRCUIT DESCRIPTION
The 8088 selects the next operating mode by latching PROM1
to logic 1 and leaving PROMO at logic 0. U190 is now located
in the top 8K of the 8088's natural 1 Mbyte address space.
This is the location that the ROM is normally in while the
Computer is in the monitor mode.
Two other options are a vailable: (1) I f P R OMO
= 1 a n d
PROM1
= 0, the ROM is placed at the top 8K of every 64K
page of memory (this is useful for the 8085, which has only
a 64K natural address space); and (2) if PROMO
= 1 a n d
PROM1 = 1, the ROM is disabled.
To select one of the above four options, the CPU must output
a data byte to port OFCH, the memory control latch. Data
bit D2 directly affects PROMO and D3 affects PROM1.
The PHANTOM* Line
The PROMSEL line from U161 also connects to U194, pin
5, an open collector buffer that connects to the PHANTOM*
line on the S-100 bus. The PHANTOM* line allows overlap-
ping blocks of memory on the S-100 bus. When properly de-
coded, the PHANTOM* line disables one block of memory
while enabling another.
In this case, whenever the monitor is selected by PROMSEL,
the PHANTOM* line goes low and all RAM locations are dis-
abled. Thus, when both PROMO and PROM1 are 0 at power-
up, the CPU reads from ROM but writes to RAM.
Since you can disable the monitor by raising both PROMO
and PROM1 to logic 1, it is possible to have continuous read/
write memory from address 0 to the top end of 16 Mbytes
(technology permitting). However, you would have to supply
your own monitor routine.