An edge 0-1 at the digital Latch input stores the current
counter value
in as
latch value
.
The status word in the input area has the following structure:
Bit
Name
Function
0
COUNT_LTCH
n
0: Value in the input image is counter value
n
1: Value in the input image is latch value
1
CTRL_C_DO
Is set when the digital output is enabled.
2
STS_SW_GATE
n
0: Software gate (SW gate) is not active
n
1: Software gate (SW gate) is active
3
reserved
reserved
4
STS_HW_GATE
n
0: Hardware gate (HW gate) is not active
n
1: Hardware gate (HW gate) is active
5
STS_I_GATE
n
0: Internal gate (I gate) is not active
n
1: Internal gate (I gate) is active
6
STS_DO
n
0: Counter output (DO) = "0"
n
1: Counter output (DO) = "1"
7
STS_C_DN
Is set at counter direction backwards.
8
STS_C_UP
Is set at counter direction forward.
9
STS_CMP*
Is set when
counter value
=
comparison value
. If com-
parison is parametrized never, the bit is never set.
10
STS_END*
Is set when
counter value
=
end value
.
11
STS_OFLW*
Is set at overflow.
12
STS_UFLW*
Is set at underflow.
13
STS_ZP*
Is set at zero-crossing.
14
STS_L
n
0: Latch input is not active
n
1: Latch input is active
15
NEW_L
Is set if value in the latch register has changed.
*) The bits remain set until reset with RES_STS (output status: bit 6).
After setting a bit in the output status word this is immediately reset. Please regard that
setting and resetting of a function at the output status word takes place with different bits.
The status word in the output area has the following structure:
Bit
Name
Function
0
GET_C_VAL
By setting the current counter value is transferred to
the process image.
1
SET_C_DO
By setting the digital output (DO) is enabled for the
counter. Then the output may only be controlled by
the counter.
2
SET_SW_GATE
By setting the software gate is set (not allowed in OB
100).
Latch value counter
X
ISTS_
X
Input status
OSTS_
X
Output status
word
VIPA System 300S
+
Deployment I/O periphery
Counter - In-/output area
HB140 | CPU | 314-6CF23 | en | 19-01
113
