YASKAWA CPU 314ST, Manual

Page: 111 / 239

The counter is controlled via the internal gate (I-gate). The I-gate is the sum of hardware-
(HW) and software-gate (SW), where the HW-gate evaluation may be deactivated via the
parametrization.
Ä
‘Gate function’ page 126
Depending on the status setting, the counter register contains the current counter value
(input status bit 0 = 0) or the current latch value (input status bit 0 = 1). By setting the
output status bit 8 the current latch value is transferred to the counter register in the input
area. By setting the output status bit 8, the current counter value is transferred.
Ä
Chap. 6.9 ‘Counter - In-/output area’ page 112
Besides of the counter register in the input area you may find a status word for every
counter in the in- respectively output area. You may monitor the status or influence the
counter by setting according bits like e.g. activate the SW gate.
Ä
‘ISTS_
X
Input status’ page 113 ,
Ä
‘OSTS_
X
Output status word’ page 113
For not all inputs are available at the same time, you may set the input assignment for
every counter via the parametrization.
Ä
‘CPU 314-6CF23: Digital part pin assignment and status indicator ’ page 95
For each counter the following inputs are available:
n Counter
x
(A)
– Pulse input for counter signal respectively track A of an encoder. Here you may
connect encoder with 1-, 2- or 4-tier evaluation.
n Counter
x
(B)
– Direction signal respectively track B of the encoder. Via the parametrization you
may invert the direction signal.
The following inputs may be assigned to a pin at the module via parametrization:
n Gate
x
– This input allows you to open the HW gate with a high peek and thus start a count
process.
n
Latch
x
– With a positive edge at Latch
x
the current counter value is stored in a memory
that you may read if needed.
n Reset
x
– As long as Reset
x
is applied with a positive level the counter is still reset to the
load value.
Every counter has an assigned output channel. Ä ‘Record set 0 - Counter mode’
page 115
The following behavior for the output channel can be set via parametrization:
n No comparison: output is not controlled
n Counter value
³
comparison value: output is set
n Counter value
£
comparison value: output is set
n Counter value = comparison value: output is set
The maximum count frequency is 100kHz, independent from the number of activated
counters.
Control counter
Read counter
Counter status word
Counter inputs (connec-
tions)
Counter outputs
Maximum count frequency
VIPA System 300S +
Deployment I/O periphery
Counter - Fast introduction
HB140 | CPU | 314-6CF23 | en | 19-01 111