Addr.
Name
Byte
Function
+30
ISTS_1
2
Input status counter 1
+32
CVCL_2
4
Counter value / latch value counter 2
+36
-
2
reserved
+38
ISTS_2
2
Input status counter 2
+40
CVCL_3
4
Counter value / latch value counter 3
+44
-
2
reserved
+46
ISTS_3
2
Input status counter 3
Used area
Addr.
Name
Byte
Function
+0
-
1
reserved
+1
DO_1
1
Digital output Q+1.0 ... Q+1.7
+10
OSTS_0
2
Output status counter 0
+12
-
2
reserved
+14
OSTS_1
2
Output status counter 1
+16
-
2
reserved
+18
OSTS_2
2
Output status counter 2
+20
-
2
reserved
+22
OSTS_3
2
Output status counter 3
6.8 Counter - Fast introduction
n
The CPU 314-6CF23 has 4 parametrizable counters integrated that may be controlled
separately.
n
Each counter is controlled via an internal gate.
n
The counter behavior and the assignment of the inputs is configurable for each
counter.
n
During the count process the counter signal is recognized and evaluated.
n
Every counter occupies one double word in the input address area with the counter
register and in the input and output area one word for the status.
By including the SPEEDBUS.GSD you may pre-set all counter parameters via a hard-
ware configuration. Except of the parameter in record set 0, you may change parameters
during runtime by using the SFC 55, 56, 57 and 58. For this you have to transfer the
wanted parameters via record set to the counter by using the according SFC in the user
application. Here you may define among others:
n
Interrupt behavior
n
Assignment I/O (Gate, Latch, Reset, OUT)
n
Input filter
n
Counter operating mode respectively behavior
n
Start value for load value, end value and comparison value register
Chap. 6.10 ‘Counter - Parametrization’ page 114
Overview
Pre-set respectively para-
metrize counter
VIPA System 300S
+
Deployment I/O periphery
Counter - Fast introduction
HB140 | CPU | 314-6CF23 | en | 19-01
110
