Toshiba TLCS-870/C Series, Manual

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11. Asynchronous Serial interface (UART )
11.2 Control
TMP86PM29BUG
11.2 Control
UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni-
tored using the UART status register (UARTSR).
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed.
Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC>
= “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s].
UART Control Register1
UARTCR1
(0025H)
7 6 5 4 3 2 1 0
TXE RXE STBT EVEN PE BRG (Initial value: 0000 0000)
TXE Transfer operation
0:
1:
Disable
Enable
Write
only
RXE Receive operation
0:
1:
Disable
Enable
STBT Transmit stop bit length
0:
1:
1 bit
2 bits
EVEN Even-numbered parity
0:
1:
Odd-numbered parity
Even-numbered parity
PE Parity addition
0:
1:
No parity
Parity
BRG Transmit clock select
000:
001:
010:
011:
100:
101:
110:
111:
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC5 ( Input INTTC5)
fc/96
UART Control Register2
UARTCR2
(0026H)
7 6 5 4 3 2 1 0
RXDNC STOPBR (Initial value: **** *000)
RXDNC
Selection of RXD input noise
rejection time
00:
01:
10:
11:
No noise rejection (Hysteresis input)
Rejects pulses shorter than 31/fc [s] as noise
Rejects pulses shorter than 63/fc [s] as noise
Rejects pulses shorter than 127/fc [s] as noise
Write
only
STOPBR Receive stop bit length
0:
1:
1 bit
2 bits