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FUNC_GPADC Registers

149

SLVUAH1C – June 2015 – Revised April 2017

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Copyright © 2015–2017, Texas Instruments Incorporated

Register Descriptions

3.13 FUNC_GPADC Registers

lists the memory-mapped registers for the FUNC_GPADC. All register offset addresses not

listed in

should be considered as reserved locations and the register contents should not be

modified.

Table 3-140. FUNC_GPADC Registers

Address

Acronym

Register Name

Section

2C0h

GPADC_CTRL1

GPADC Control Register
RESET register domain: HWRST

2C2h

GPADC_FLUSH

GPADC FLUSH register
RESET register domain: HWRST

2C3h

GPADC_AUTO_CTRL

GPADC Automatic Control register (Periodic)
RESET register domain: HWRST

2C4h

GPADC_STATUS

GPADC Status Register
RESET register domain: HWRST

2C5h

GPADC_FLUSH_EN

GPADC FLSUH Enable register
RESET register domain: HWRST

2C7h

GPADC_STUCK

GPADC stuck status
RESET register domain: HWRST

2C8h

GPADC_AUTO_SELECT

GPADC Automatic (Periodic) Channel selection for
Conversion 0 and Conversion 1
RESET register domain: HWRST
Note: All Selected channels are queued and converted
from channel 0 to 11
The first (lower) converted channel results is placed in
GPADC_AUTO_CONV0 register and the second one is
placed in GPADC_AUTO_CONV0 register.
It is why it is recommended to put the lower channel to
convert in AUTO_CONV0_SEL and the higher channel
to convert in AUTO_CONV0_SEL.

2C9h

GPADC_AUTO_CONV0_LSB

GPADC data results of the Automatic (Periodic)
conversion 0 (LSB)
RESET register domain: HWRST

2CAh

GPADC_AUTO_CONV0_MSB

GPADC data results of the Automatic (Periodic)
conversion 0 (MSB)
RESET register domain: HWRST

2CBh

GPADC_AUTO_CONV1_LSB

GPADC data results of the Automatic (Periodic)
conversion 1 (LSB)
RESET register domain: HWRST

Section 3.13.10

2CCh

GPADC_AUTO_CONV1_MSB

GPADC data results of the Automatic (Periodic)
conversion 1 (MSB)
RESET register domain: HWRST

Section 3.13.11

2CDh

GPADC_SW_SELECT

GPADC Software Channel selection for Conversion 0
RESET register domain: HWRST

Section 3.13.12

2CEh

GPADC_SW_CONV0_LSB

GPADC data results of the Software conversion 0 (LSB)
RESET register domain: HWRST

Section 3.13.13

2CFh

GPADC_SW_CONV0_MSB

GPADC data results of the Software conversion 0 (MSB)
RESET register domain: HWRST

Section 3.13.14

2D0h

GPADC_THRES_CONV0_LSB

LSB of Threshold reference to be compared to the
Conversion 0 results
RESET register domain: HWRST

Section 3.13.15

2D1h

GPADC_THRES_CONV0_MSB

MSB of Threshold reference to be compared to the
Conversion 0 results
RESET register domain: HWRST

Section 3.13.16

2D2h

GPADC_THRES_CONV1_LSB

LSB of Threshold reference to be compared to the
Conversion 1 results
RESET register domain: HWRST

Section 3.13.17

2D3h

GPADC_THRES_CONV1_MSB

MSB of Threshold reference to be compared to the
Conversion 1 results
RESET register domain: HWRST

Section 3.13.18

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Summary of Contents for TPS65917-Q1

Page 1: ...TPS65917 Q1 Register Map Technical Reference Manual Literature Number SLVUAH1C June 2015 Revised April 2017 ...

Page 2: ...number of the register and AA stands for the register address within the memory page The page numbers are mapped to the slave device address as following Page 0x0 Slave Device address 0x12 for DVS registers Page 0x1 Slave Device address 0x48 or 0x58 for Power registers Page 0x2 Slave Device address 0x49 or 0x59 for Interfaces and Auxiliaries registers Page 0x3 Slave Device address 0x4A or 0x5A for...

Page 3: ...SMPS_DVS 0x020 32 Bytes FUNC_BACKUP 0x118 8 Bytes FUNC_SMPS 0x120 48 Bytes FUNC_LDO 0x150 47 Bytes FUNC_SPI 0x17F 1 Byte FUNC_DVFS 0x180 8 Bytes FUNC_PMU_CONTROL 0x1A0 32 Bytes FUNC_RESOURCE 0x1D4 28 Bytes FUNC_PAD_CONTROL 0x1F0 16 Bytes FUNC_INTERRUPT 0x210 32 Bytes FUNC_ID 0x24F 4 Bytes FUNC_GPIO 0x280 20 Bytes FUNC_GPADC 0x2C0 32 Bytes FUNC_DESIGNREV 0x357 1 Byte FUNC_TRIM_GPADC 0x3CD 18 Bytes ...

Page 4: ...nfig RESET register domain SWORST Section 3 1 1 23h SMPS1_VOLTAGE SMPS1 or SMPS12 in case of dual phase DVS register Voltage to apply to the resource when it is not a DVS force command OTP_Config r RESET register domain SWORST Section 3 1 2 26h SMPS2_FORCE SMPS2 DVS register Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Section 3 1 3 27h SM...

Page 5: ... phase DVS register Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Figure 3 1 SMPS1_FORCE Register 7 6 5 4 3 2 1 0 CMD VSEL R W 1h R W X Table 3 2 SMPS1_FORCE Register Field Descriptions Bit Field Type Reset Description 7 CMD R W 1h DVS command register selection When 0 SMPS1_FORCE VSEL voltage is applied When 1 SMPS1_VOLTAGE VSEL voltage is...

Page 6: ... resource when it is not a DVS force command OTP_Config r RESET register domain SWORST Figure 3 2 SMPS1_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 3 SMPS1_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS1_VOLTAGE VSEL and SPMS1_FORCE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RANGE bit is RO w...

Page 7: ...gister Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Figure 3 3 SMPS2_FORCE Register 7 6 5 4 3 2 1 0 CMD VSEL R W 1h R W X Table 3 4 SMPS2_FORCE Register Field Descriptions Bit Field Type Reset Description 7 CMD R W 1h DVS command register selection When 0 SMPS2_FORCE VSEL voltage is applied When 1 SMPS2_VOLTAGE VSEL voltage is applied defa...

Page 8: ...ister Voltage to apply to the resource when it is not a DVS force command OTP_Config RESET register domain SWORST Figure 3 4 SMPS2_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 5 SMPS2_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS2_VOLTAGE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RANGE bit i...

Page 9: ...ter Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Figure 3 5 SMPS3_FORCE Register 7 6 5 4 3 2 1 0 CMD VSEL R W 1h R W X Table 3 6 SMPS3_FORCE Register Field Descriptions Bit Field Type Reset Description 7 CMD R W 1h DVS command register selection When 0 SMPS3_FORCE VSEL voltage is applied When 1 SMPS3_VOLTAGE VSEL voltage is applied default...

Page 10: ... to apply to the resource when it is not a DVS force command OTP_Config RESET register domain SWORST Figure 3 6 SMPS3_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 7 SMPS3_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS3_VOLTAGE VSEL and SPMS3_FORCE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RAN...

Page 11: ... These registers will retain their content as long as VRTC is active RESET register domain POR Section 3 2 3 11Bh BACKUP3 Backup register 3 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Section 3 2 4 11Ch BACKUP4 Backup register 4 which can be used for stor...

Page 12: ... shown in Figure 3 7 and described in Table 3 9 Return to Summary Table Backup register 0 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 7 BACKUP0 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 9 BACKUP0 Register Field Descriptions Bit Field Type Re...

Page 13: ...shown in Figure 3 8 and described in Table 3 10 Return to Summary Table Backup register 1 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 8 BACKUP1 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 10 BACKUP1 Register Field Descriptions Bit Field Type R...

Page 14: ...shown in Figure 3 9 and described in Table 3 11 Return to Summary Table Backup register 2 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 9 BACKUP2 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 11 BACKUP2 Register Field Descriptions Bit Field Type R...

Page 15: ...hown in Figure 3 10 and described in Table 3 12 Return to Summary Table Backup register 3 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 10 BACKUP3 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 12 BACKUP3 Register Field Descriptions Bit Field Type ...

Page 16: ...hown in Figure 3 11 and described in Table 3 13 Return to Summary Table Backup register 4 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 11 BACKUP4 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 13 BACKUP4 Register Field Descriptions Bit Field Type ...

Page 17: ...hown in Figure 3 12 and described in Table 3 14 Return to Summary Table Backup register 5 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 12 BACKUP5 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 14 BACKUP5 Register Field Descriptions Bit Field Type ...

Page 18: ...hown in Figure 3 13 and described in Table 3 15 Return to Summary Table Backup register 6 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 13 BACKUP6 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 15 BACKUP6 Register Field Descriptions Bit Field Type ...

Page 19: ...hown in Figure 3 14 and described in Table 3 16 Return to Summary Table Backup register 7 which can be used for storage by the application firmware when the external host is power down These registers will retain their content as long as VRTC is active RESET register domain POR Figure 3 14 BACKUP7 Register 7 6 5 4 3 2 1 0 BACKUP R W 0h Table 3 16 BACKUP7 Register Field Descriptions Bit Field Type ...

Page 20: ...nfig RESET register domain SWORST Section 3 3 3 124h SMPS2_CTRL SMPS2 control register RESET register domain HWRST MODE_ACTIVE and MODE_SLEEP are in SWORST domain Notes MODE_SLEEP is used when NSLEEP ENABLE1 ENABLE2 signals select the resource MODE_ACTIVE is used when none of NSLEEP ENABLE1 ENABLE2 signals select resource see Resources SLEEP ACTIVE assignments table in the Data Manual for details ...

Page 21: ...pply to the resource RESET register domain SWORST Section 3 3 13 144h SMPS_CTRL SMPS control register RESET register domain HWRST Section 3 3 14 145h SMPS_PD_CTRL SMPS Pull Down enable register RESET register domain HWRST Notes SMPS pull down register bits validate the control of the active discharge of each power resource to full fill the turn off timing requirements When a pull down is not enabl...

Page 22: ...EP MODE_ACTIVE R W 0h R W 0h R 0h R W 0h R W 0h Table 3 18 SMPS1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default value from OTP in SMPS1_VOLTAGE VSEL and SMPS1_FORCE VSEL register and re load the default value reset value in SMPS1_FORCE CMD during Warm Reset 1 Maintain current voltage during Warm Reset Registers remain un...

Page 23: ...al phase DVS register Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Figure 3 16 SMPS1_FORCE Register 7 6 5 4 3 2 1 0 CMD VSEL R W 1h R W X Table 3 19 SMPS1_FORCE Register Field Descriptions Bit Field Type Reset Description 7 CMD R W 1h DVS command register selection When 0 SMPS1_FORCE VSEL voltage is applied When 1 SMPS1_VOLTAGE VSEL voltag...

Page 24: ...y to the resource when it is not a DVS force command OTP_Config RESET register domain SWORST Figure 3 17 SMPS1_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 20 SMPS1_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS1_VOLTAGE VSEL and SMPS1_FORCE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RANGE bit...

Page 25: ... 1010000 1 24V 2 48V 0010001 0 61V 1 22V 1010001 1 25V 2 5V 0010010 0 62V 1 24V 1010010 1 26V 2 52V 0010011 0 63V 1 26V 1010011 1 27V 2 54V 0010100 0 64V 1 28V 1010100 1 28V 2 56V 0010101 0 65V 1 3V 1010101 1 29V 2 58V 0010110 0 66V 1 32V 1010110 1 3V 2 6V 0010111 0 67V 1 34V 1010111 1 31V 2 62V 0011000 0 68V 1 36V 1011000 1 32V 2 64V 0011001 0 69V 1 38V 1011001 1 33V 2 66V 0011010 0 70V 1 4V 1011...

Page 26: ...6V 1110001 1 57V 3 14V 0110010 0 94V 1 88V 1110010 1 58V 3 16V 0110011 0 95V 1 90V 1110011 1 59V 3 18V 0110100 0 96V 1 92V 1110100 1 6V 3 2V 0110101 0 97V 1 94V 1110101 1 61V 3 22V 0110110 0 98V 1 96V 1110110 1 62V 3 24V 0110111 0 99V 1 98V 1110111 1 63V 3 26V 0111000 1 00V 2V 1111000 1 64V 3 28V 0111001 1 01V 2 02V 1111001 1 65V 3 3V 0111010 1 02V 2 04V 1111010 1 65V 3 3V 0111011 1 03V 2 06V 1111...

Page 27: ...8 SMPS2_CTRL Register 7 6 5 4 3 2 1 0 WR_S ROOF_FLOOR _EN STATUS MODE_SLEEP MODE_ACTIVE R W 0h R W 0h R 0h R W 0h R W 0h Table 3 21 SMPS2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default value from OTP in SMPS2_VOLTAGE VSEL register during Warm Reset 1 Maintain current voltage during Warm Reset Registers remain unchanged n...

Page 28: ...ister Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Figure 3 19 SMPS2_FORCE Register 7 6 5 4 3 2 1 0 CMD VSEL R W 1h R W X Table 3 22 SMPS2_FORCE Register Field Descriptions Bit Field Type Reset Description 7 CMD R W 1h DVS command register selection When 0 SMPS2_FORCE VSEL voltage is applied When 1 SMPS2_VOLTAGE VSEL voltage is applied def...

Page 29: ...ster Voltage to apply to the resource when it is not a DVS force command OTP_Config RESET register domain SWORST Figure 3 20 SMPS2_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 23 SMPS2_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS2_VOLTAGE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RANGE bit ...

Page 30: ...S ROOF_FLOOR _EN STATUS MODE_SLEEP MODE_ACTIVE R W 0h R W 0h R 0h R W 0h R W 0h Table 3 24 SMPS3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default value from OTP in SMPS3_VOLTAGE VSEL and SMPS3_FORCE VSEL register and re load the default value reset value in SMPS3_FORCE CMD during Warm Reset 1 Maintain current voltage durin...

Page 31: ...ister Voltage to apply to the resource when it is a DVS force command OTP_Config RESET register domain SWORST Figure 3 22 SMPS3_FORCE Register 7 6 5 4 3 2 1 0 CMD VSEL R W 1h R W X Table 3 25 SMPS3_FORCE Register Field Descriptions Bit Field Type Reset Description 7 CMD R W 1h DVS command register selection When 0 SMPS3_FORCE VSEL voltage is applied When 1 SMPS3_VOLTAGE VSEL voltage is applied def...

Page 32: ...ge to apply to the resource when it is not a DVS force command OTP_Config RESET register domain SWORST Figure 3 23 SMPS3_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 26 SMPS3_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS3_VOLTAGE VSEL and SMPS3_FORCE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note...

Page 33: ...ource see Resources SLEEP ACTIVE assignments table in the Data Manual for details Figure 3 24 SMPS4_CTRL Register 7 6 5 4 3 2 1 0 WR_S RESERVED STATUS MODE_SLEEP MODE_ACTIVE R W 0h R 0h R 0h R W 0h R W 0h Table 3 27 SMPS4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default value from OTP in SMPS4_VOLTAGE VSEL register during ...

Page 34: ...mmary Table SMPS4 register Voltage to apply to the resource RESET register domain SWORST Figure 3 25 SMPS4_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 28 SMPS4_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS4_VOLTAGE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RANGE bit is RO when SMPS4 is ON R...

Page 35: ...ource see Resources SLEEP ACTIVE assignments table in the Data Manual for details Figure 3 26 SMPS5_CTRL Register 7 6 5 4 3 2 1 0 WR_S RESERVED STATUS MODE_SLEEP MODE_ACTIVE R W 0h R 0h R 0h R W 0h R W 0h Table 3 29 SMPS5_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default value from OTP in SMPS5_VOLTAGE VSEL register during ...

Page 36: ...mmary Table SMPS5 register Voltage to apply to the resource RESET register domain SWORST Figure 3 27 SMPS5_VOLTAGE Register 7 6 5 4 3 2 1 0 RANGE VSEL R W X R W X Table 3 30 SMPS5_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 RANGE R W X Range of the VSEL voltage This bit is applied to SMPS5_VOLTAGE VSEL 0 0 5V to 1 65V 1 1 0 to 3 3V Note RANGE bit is RO when SMPS5 is ON R...

Page 37: ...Table 3 31 SMPS_CTRL Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 RESERVED R 0h 4 SMPS1_SMPS12_EN R X Selection of the type of configuration of the SMPS12 0 SMPS1 single phase SMPS2 single phase 1 SMPS12 dual phase 3 2 RESERVED R 0h 1 0 SMPS12_PHASE_CTRL R W 0h Selection of the phase mode of the SMPS12 SMPS1 Single Phase SMPS2 Single Phase configuration or SMPS1...

Page 38: ...that the device restart correctly at the next power up sequence Figure 3 29 SMPS_PD_CTRL Register 7 6 5 4 3 2 1 0 RESERVED SMPS5 RESERVED SMPS4 SMPS3 RESERVED SMPS2 SMPS1 R 0h R W 1h R 0h R W 1h R W 1h R 0h R W 1h R W 1h Table 3 32 SMPS_PD_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SMPS5 R W 1h 0 Pull down is disabled 1 Pull down is enabled when SPMS5 is in...

Page 39: ... 1 0 RESERVED SMPS5 RES ERV ED RESERVED SMPS3 RESERVED RESERVED SMPS12 R 1h R W 1h R 1h R 1h R W 1h R 1h R 1h R W 1h Table 3 33 SMPS_THERMAL_EN Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 1h 6 SMPS5 R W 1h 0 SMPS5 Thermal feature is not enabled 1 SMPS5 Thermal feature is enabled default 5 RESERVED R 1h 4 RESERVED R 1h 3 SMPS3 R W 1h 0 SMPS3 Thermal feature is not enab...

Page 40: ... SMPS3 RESERVED RESERVED SMPS12 R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h Table 3 34 SMPS_THERMAL_STATUS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SMPS5 R 0h 0 SMPS5 Thermal measurement is below the limit SMPS is functional 1 SMPS5 Thermal measurement is over the limit see specification 5 RESERVED R 0h 4 RESERVED R 0h 3 SMPS3 R 0h 0 SMPS3 Thermal measurement is b...

Page 41: ... 0h R 0h R 0h R 0h Table 3 35 SMPS_SHORT_STATUS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SMPS5 R 0h 0 SMPS5 is functional No short detected default 1 SMPS5 output is shorted 5 RESERVED R 0h 4 SMPS4 R 0h 0 SMPS4 is functional No short detected default 1 SMPS4 output is shorted 3 SMPS3 R 0h 0 SMPS3 is functional No short detected default 1 SMPS3 output is shorte...

Page 42: ...N Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 1h 6 SMPS5 R W 1h 0 SMPS5 Negative Current comparator for measurement is not enabled 1 SMPS5 Negative Current comparator for measurement is enabled default 5 RESERVED R 1h 4 SMPS4 R W 1h 0 SMPS4 Negative Current comparator for measurement is not enabled 1 SMPS4 Negative Current comparator for measurement is enabled default...

Page 43: ...e SMPS5 state is generated on POWERGOOD line 1 SMPS5 line is masked No SMPS5 state is generated on POWERGOOD line default 5 RESERVED R 0h 4 SMPS4 R W 1h SMPS4 POWERGOOD Mask bit register 0 SMPS4 line is enabled The SMPS4 state is generated on POWERGOOD line 1 SMPS4 line is masked No SMPS4 state is generated on POWERGOOD line default 3 SMPS3 R W 1h SMPS3 POWERGOOD Mask bit register 0 SMPS3 line is ...

Page 44: ... POWERGOOD _TYPE_SELEC T RESERVED OVC_ALARM RESERVED RESERVED RESERVED RESERVED R W 0h R 0h R W 1h R 0h R 0h R 0h R 0h Table 3 38 SMPS_POWERGOOD_MASK2 Register Field Descriptions Bit Field Type Reset Description 7 POWERGOOD_TYPE_S ELECT R W 0h Selection of the POWERGOOD type of monitoring 0 Voltage monitoring above threshold AND Current monitoring over current default 1 Current monitoring only ove...

Page 45: ...S PLL control register RESET register domain HWRST Figure 3 36 SMPS_PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED PLL_EN_BYPA SS PLL_BYPASS_ CLK RESERVED RESERVED R 0h R W 0h R W 0h R 0h R 0h Table 3 39 SMPS_PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 PLL_EN_BYPASS R W 0h Enable disable the bypass mode 0 No Bypass default 1 Bypass is enabled 2 PLL_BYPASS_...

Page 46: ...s table in the Data Manual for details Section 3 4 3 153h LDO2_VOLTAGE LDO2 Voltage selection OTP_Config RESET register domain SWORST Section 3 4 4 154h LDO3_CTRL LDO3 control register RESET register domain HWRST MODE_ACTIVE and MODE_SLEEP are in SWORST domain MODE_SLEEP is used when NSLEEP ENABLE1 ENABL2 signals select the resource MODE_ACTIVE is used when none of NSLEEP ENABLE1 ENABL2 signals se...

Page 47: ...rn off timing requirements When a pull down is not enabled there is always a weak pull down present at the output of the power resource so that the device restarts correctly at the next power up sequence Section 3 4 12 16Dh LDO_SHORT_STATUS1 LDO Short circuit status register 1 At Power On LDO short input informations are masked during 1 ms This 1 ms masking is activated and re started each time on...

Page 48: ...a Manual for details Figure 3 37 LDO1_CTRL Register 7 6 5 4 3 2 1 0 WR_S LDO_BYPASS _EN RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R W 0h R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h Table 3 41 LDO1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default LDO1_VOLTAGE register value during Warm Reset 1 Maintain current ...

Page 49: ...FF 0 9V to 3 3V 000000 0V 100000 2 45V 000001 0 9V 100001 2 5V 000010 0 95V 100010 2 55V 000011 1V 100011 2 6V 000100 1 05V 100100 2 65V 000101 1 1V 100101 2 7V 000110 1 15V 100110 2 75V 000111 1 2V 100111 2 8V 001000 1 25V 101000 2 85V 001001 1 3V 101001 2 9V 001010 1 35V 101010 2 95V 001011 1 4V 101011 3V 001100 1 45V 101100 3 05V 001101 1 5V 101101 3 1V 001110 1 55V 101110 3 15V 001111 1 6V 101...

Page 50: ...nments table in the Data Manual for details Figure 3 39 LDO2_CTRL Register 7 6 5 4 3 2 1 0 WR_S LDO_BYPASS _EN RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R W 0h R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h Table 3 43 LDO2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default LDO2_VOLTAGE register value during Warm Re...

Page 51: ...3h reset X LDO2_VOLTAGE is shown in Figure 3 40 and described in Table 3 44 Return to Summary Table LDO2 Voltage selection OTP_Config RESET register domain SWORST Figure 3 40 LDO2_VOLTAGE Register 7 6 5 4 3 2 1 0 RESERVED VSEL R 0h R W X Table 3 44 LDO2_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 0 VSEL R W X See VSEL cross table showed in LDO1_VOLTAGE ...

Page 52: ...source MODE_ACTIVE is used when none of NSLEEP ENABLE1 ENABL2 signals select the resource Figure 3 41 LDO3_CTRL Register 7 6 5 4 3 2 1 0 WR_S RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h Table 3 45 LDO3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity 0 Re load the default LDO3_VOLTAGE regis...

Page 53: ...5h reset X LDO3_VOLTAGE is shown in Figure 3 42 and described in Table 3 46 Return to Summary Table LDO3 Voltage selection OTP_Config RESET register domain SWORST Figure 3 42 LDO3_VOLTAGE Register 7 6 5 4 3 2 1 0 RESERVED VSEL R 0h R W X Table 3 46 LDO3_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 0 VSEL R W X See VSEL cross table showed in LDO1_VOLTAGE ...

Page 54: ...ABLE1 ENABLE2 signals select resource see Resources SLEEP ACTIVE assignments table in the Data Manual for details Figure 3 43 LDO4_CTRL Register 7 6 5 4 3 2 1 0 WR_S RESERVED RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R W 0h R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h Table 3 47 LDO4_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity ...

Page 55: ...Fh reset X LDO4_VOLTAGE is shown in Figure 3 44 and described in Table 3 48 Return to Summary Table LDO4 Voltage selection OTP_Config RESET register domain SWORST Figure 3 44 LDO4_VOLTAGE Register 7 6 5 4 3 2 1 0 RESERVED VSEL R 0h R W X Table 3 48 LDO4_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 0 VSEL R W X See VSEL cross table showed in LDO1_VOLTAGE ...

Page 56: ...one of NSLEEP ENABLE1 ENABLE2 signals select resource see Resources SLEEP ACTIVE assignments table in the Data Manual for details Figure 3 45 LDO5_CTRL Register 7 6 5 4 3 2 1 0 WR_S RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h Table 3 49 LDO5_CTRL Register Field Descriptions Bit Field Type Reset Description 7 WR_S R W 0h Warm reset sensitivity ...

Page 57: ...63h reset X LDO5_VOLTAGE is shown in Figure 3 46 and described in Table 3 50 Return to Summary Table LDO5 Voltage selection OTP_Config RESET register domain SWORST Figure 3 46 LDO5_VOLTAGE Register 7 6 5 4 3 2 1 0 RESERVED VSEL R 0h R W X Table 3 50 LDO5_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 0 VSEL R W X See VSEL cross table showed in LDO1_VOLTAGE...

Page 58: ...own is not enabled there is always a weak pull down present at the output of the power resource so that the device restarts correctly at the next power up sequence Figure 3 47 LDO_PD_CTRL1 Register 7 6 5 4 3 2 1 0 LDO4 RESERVED RESERVED RESERVED RESERVED RESERVED LDO2 LDO1 R W 1h R 0h R 0h R 0h R 0h R 0h R W 1h R W 1h Table 3 51 LDO_PD_CTRL1 Register Field Descriptions Bit Field Type Reset Descrip...

Page 59: ...iming requirements When a pull down is not enabled there is always a weak pull down present at the output of the power resource so that the device restarts correctly at the next power up sequence Figure 3 48 LDO_PD_CTRL2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED LDO3 LDO5 RESERVED R 0h R 0h R 0h R 0h R 0h R W 1h R W 1h R 0h Table 3 52 LDO_PD_CTRL2 Register Field Descrip...

Page 60: ...e started each time one LDO is enabled RESET register domain POR Figure 3 49 LDO_SHORT_STATUS1 Register 7 6 5 4 3 2 1 0 LDO4 RESERVED RESERVED RESERVED RESERVED RESERVED LDO2 LDO1 R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h Table 3 53 LDO_SHORT_STATUS1 Register Field Descriptions Bit Field Type Reset Description 7 LDO4 R 0h 0 LDO4 is functional No short detected default 1 LDO4 output is short detected...

Page 61: ...2 RESET register domain POR Figure 3 50 LDO_SHORT_STATUS2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED LDO3 LDO5 RESERVED R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h Table 3 54 LDO_SHORT_STATUS2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R 0h 3 RESERVED R 0h 2 LDO3 R 0h 0 LDOUSB is functional No short...

Page 62: ...egister bits validate the control of the active discharge of each power resource to fulfill the turn off timing requirements When a pull down is not enabled there is always a weak pull down present at the output of the power resource so that the device restarts correctly at the next power up sequence Figure 3 51 LDO_PD_CTRL3 Register 7 6 5 4 3 2 1 0 LDOVANA RESERVED RESERVED R W 1h R 0h R 0h Table...

Page 63: ...3 52 and described in Table 3 56 Return to Summary Table LDO short circuit status register 3 RESET register domain POR Figure 3 52 LDO_SHORT_STATUS3 Register 7 6 5 4 3 2 1 0 LDOVANA RESERVED RESERVED R 0h R 0h R 0h Table 3 56 LDO_SHORT_STATUS3 Register Field Descriptions Bit Field Type Reset Description 7 LDOVANA R 0h LDOVANA internal LDO reserved 0 LDOVANA is functional No short detected default ...

Page 64: ...able 3 57 lists the memory mapped registers for the FUNC_SPI All register offset addresses not listed in Table 3 57 should be considered as reserved locations and the register contents should not be modified Table 3 57 FUNC_SPI Registers Address Acronym Register Name Section 17Fh SPI_PAGE_CTRL SPI Page Control register used only when SPI interface is used RESET register domain SWORST Section 3 5 1...

Page 65: ... and described in Table 3 58 Return to Summary Table SPI Page Control register used only when SPI interface is used RESET register domain SWORST Figure 3 53 SPI_PAGE_CTRL Register 7 6 5 4 3 2 1 0 RESERVED SPI_PAGE_AC CESS R 0h R W 0h Table 3 58 SPI_PAGE_CTRL Register Field Descriptions Bit Field Type Reset Description 7 1 RESERVED R 0h 0 SPI_PAGE_ACCESS R W 0h Page selection for SPI interface only...

Page 66: ...ted in Table 3 59 should be considered as reserved locations and the register contents should not be modified Table 3 59 FUNC_DVFS Registers Address Acronym Register Name Section 180h SMPS_DVFS_CTRL SMPS DVFS control register RESET register domain SWORST excepted DVFS_SMPS_SELECT bit 4 on POR Section 3 6 1 181h SMPS_DVFS_VOLTAGE_MAX SMPS DVFS maximum voltage register RESET register domain HWRST Se...

Page 67: ...put voltage upon OFF to ACTIVE transition controlled with ENABLE2 pins 0 upon OFF to ACTIVE transition controlled with ENABLE2 pins SMPS12 output voltage is set by SMPS12_VOLTAGE VSEL register 1 upon OFF to ACTIVE transition controlled with ENABLE2 pins SMPS12 output voltage is set with the latest voltage sum result of the Offset value computed on PWM_DAT signal plus SMPS12_FORCE VSEL register bef...

Page 68: ... RESET register domain HWRST Figure 3 55 SMPS_DVFS_VOLTAGE_MAX Register 7 6 5 4 3 2 1 0 LOCK VOLTAGE_MAX R W 0h R W 0h Table 3 61 SMPS_DVFS_VOLTAGE_MAX Register Field Descriptions Bit Field Type Reset Description 7 LOCK R W 0h Access protection of the DVFS1_VOLTAGE_MAX register 0 No protection R W access to these register bits 1 Protection of these registers Read only This bit will reset 0b0 durin...

Page 69: ...DVFS status register RESET register domain HWRST Figure 3 56 SMPS_DVFS_STATUS Register 7 6 5 4 3 2 1 0 RESERVED OFFSET_STATUS R 0h R 0h Table 3 62 SMPS_DVFS_STATUS Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 0 OFFSET_STATUS R 0h Offset status register between 0 and 32 in decimal SMPS_DVFS_CTRL DVFS1_OFFSET_STEP 0 x1 multiplier 10mv per step 1 x2 multiplier 20mV...

Page 70: ...OG TIMER counter starts as soon as RESET_OUT is released Section 3 7 5 1A8h VRTC_CTRL VRTC Control Register RESET register domain HWRST Section 3 7 6 1A9h LONG_PRESS_KEY Long Press Key LPK configuration register RESET register domain HWRST Section 3 7 7 1AAh OSC_THERM_CTRL Oscillator and Thermal control register RESET register domain HWRST Section 3 7 8 1AFh SWOFF_HWRST Qualify which switch off ev...

Page 71: ...ed OSC_FAILURE on POR Figure 3 57 DEV_CTRL Register 7 6 5 4 3 2 1 0 RESERVED DEV_STATUS SW_RST DEV_ON R 0h R 0h R W 0h R W 1h Table 3 64 DEV_CTRL Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 2 DEV_STATUS R 0h Device status 00 OFF 01 ACTIVE 10 Not applicable ACTIVE 11 SLEEP 1 SW_RST R W 0h Software Reset SW_RST Writing 1 will restart the device turn off sequence ...

Page 72: ...R W 1h R W 1h R W 1h Table 3 65 POWER_CTRL Register Field Descriptions Bit Field Type Reset Description 7 3 RESERVED R 0h 2 ENABLE2_MASK R W 1h Enable of the ENABLE2 line mask 0 ENABLE2 is not masked allow control of the resource with ENABLE2 pin 1 ENABLE2 is masked does not affect resource control default 1 ENABLE1_MASK R W 1h Enable of the ENABLE1 line mask 0 ENABLE1 is not masked allow control ...

Page 73: ...ld Type Reset Description 7 5 RESERVED R 0h 4 0 THRESHOLD R X VSYS_LO System voltage falling edge threshold When VCCx input falls below VSYS_LO device enters OFF mode and is ready for start up event Configured by OTP bits From 2 5V to 3 10V per 50mV step 00000 2 300 V Reserved 00001 2 050 V Reserved 00010 2 100 V Reserved 00011 2 150 V Reserved 00100 2 200 V Reserved 00101 2 250 V Reserved 00110 2...

Page 74: ...YS Monitoring register This register is initialized by OTP memory VSYS_HI from 2 5V to 3 85V only The software can overwrite this value by a new value VSYS_MON from 2 3V to 4 6V RESET register domain SWORST Figure 3 60 VSYS_MON Register 7 6 5 4 3 2 1 0 ENABLE RESERVED THRESHOLD R W 0h R 0h R W X Table 3 67 VSYS_MON Register Field Descriptions Bit Field Type Reset Description 7 ENABLE R W 0h Enable...

Page 75: ...0101 3 85 V 000110 2 30 V 100110 3 90 V 000111 2 35 V 100111 3 95 V 001000 2 40 V 101000 4 00 V 001001 2 45 V 101001 4 05 V 001010 2 50 V 101010 4 10 V 001011 2 55 V 101011 4 15 V 001100 2 60 V 101100 4 20 V 001101 2 65 V 101101 4 25 V 001110 2 70 V 101110 4 30 V 001111 2 75 V 101111 4 35 V 010000 2 80 V 110000 4 40 V 010001 2 85 V 110001 4 45 V 010010 2 90 V 110010 4 50 V 010011 2 95 V 110011 4 5...

Page 76: ...OG Register 7 6 5 4 3 2 1 0 RESERVED LOCK ENABLE MODE TIMER R 0h R W 0h R W 0h R W 0h R W 7h Table 3 68 WATCHDOG Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 LOCK R W 0h Access protection of the WATCHDOG ENABLE WATCHDOC MODE and WATCHDOG LOCK bits 0 No protection R W access to these register bits 1 Protection of these registers Read only This bit will reset 0b0 ...

Page 77: ...e selection This bit will allow to decrease the power consumption in BACKUP mode by setting the VRTC at 1 5V 0 1 8V default 1 1 5V 6 VRTC_EN_SLP R W 1h 0 VRTC is configured in the standard power mode configuration when device is in SLEEP state biasing also in SLEEP state 1 VRTC is configured in a low power mode configuration when device is in SLEEP state biasing also in SLEEP state default 5 VRTC_...

Page 78: ...3 LONG_PRESS_KEY Register 7 6 5 4 3 2 1 0 LPK_LOCK RESERVED RESERVED RESERVED LPK_TIME RESERVED R W 0h R 0h R 1h R 1h R W 3h R 0h Table 3 70 LONG_PRESS_KEY Register Field Descriptions Bit Field Type Reset Description 7 LPK_LOCK R W 0h Access protection of the LPK_TIME LPK_EN and LPK_LOCK registers 0 No protection R W access to these register bits default 1 Protection of these registers Read only T...

Page 79: ...fault 1 VANA LDO is ON in SLEEP mode In case some modules are used in SLEEP mode and need VANA ILMON 6 INT_MASK_IN_SLEEP R W 0h INT masked selection during SLEEP mode Released interrupt line only when DEVICE fully wake up 0 INT is not masked in SLEEP mode default 1 INT is asserted when SLEEP2ACTIVE transition is completed allow to wakeup platform before INT generation 5 RC15MHZ_ON_IN_SLEE P R W 0h...

Page 80: ... WTD TSHUT RESET_IN SW_RST VSYS_LO GPADC_SHUT DOWN R X R X R X R X R X R X R X R X Table 3 72 SWOFF_HWRST Register Field Descriptions Bit Field Type Reset Description 7 PWRON_LPK R X 0 Masked Switchoff reset 1 Not masked Hardware reset 6 PWRDOWN R X 0 Masked Switchoff reset 1 Not masked Hardware reset 5 WTD R X 0 Masked Switchoff reset 1 Not masked Hardware reset 4 TSHUT R X 0 Masked Switchoff res...

Page 81: ... 2 1 0 PWRON_LPK PWRDOWN WTD TSHUT RESET_IN SW_RST VSYS_LO GPADC_SHUT DOWN R W X R W X R W X R W X R W X R W X R W X R W X Table 3 73 SWOFF_COLDRST Register Field Descriptions Bit Field Type Reset Description 7 PWRON_LPK R W X 0 Masked Shutdown 1 Not masked Cold restart 6 PWRDOWN R W X 0 Masked Shutdown 1 Not masked Cold restart 5 WTD R W X 0 Masked Shutdown 1 Not masked Cold restart 4 TSHUT R W X...

Page 82: ...us register registers switch off event RESET register domain PORRST Figure 3 67 SWOFF_STATUS Register 7 6 5 4 3 2 1 0 PWRON_LPK PWRDOWN WTD TSHUT RESET_IN SW_RST VSYS_LO GPADC_SHUT DOWN RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h Table 3 74 SWOFF_STATUS Register Field Descriptions Bit Field Type Reset Description 7 PWRON_LPK RC 0h 6 PWRDOWN RC 0h 5 WTD RC 0h 4 TSHUT RC 0h 3 RESET_IN RC 0h 2 SW...

Page 83: ...hen VCC_SENSE is 5V 0 VCC_SENSE input buffer is not enabled 1 VCC_SENSE input buffer is enabled 5 4 PLL_AUTO_CTRL R W X Enable disable PLL under different device mode 00 PLL is not enabled disabled automatically PLL enable command should be stored in OTP for power sequence 01 Enable PLL in ACTIVE mode at the start point of OFF2ACT transition Disabled at the end point of ACT2OFF 10 Enable PLL in SL...

Page 84: ...PMU_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7 SPARE7 R W X 6 SPARE6 R W X 5 SPARE5 R W X 4 SPARE4 R W X 3 INT_LINE_DIS R W X Interrupt line INT output buffer configuration 0 Normal operation standard buffer OD or PP 1 INT output buffer is high impedance with an internal pull up to VIO enabled 2 WDT_HOLD_IN_SLEEP R W X 0 primary watchdog timer continues to run in device s...

Page 85: ...ster 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED FSD_INT_SRC RESERVED RESERVED RESERVED FSD_MASK R 0h R 0h R 0h RC 0h R 0h R 0h R 0h R W X Table 3 77 PMU_SECONDARY_INT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 FSD_INT_SRC RC 0h First Supply Detection FSD interrupt status source 0 First Supply Detection FSD is not the source of int...

Page 86: ...ss 1B7h reset X SW_REVISION is shown in Figure 3 71 and described in Table 3 78 Return to Summary Table Software SW revision register RESET register domain HWRST Figure 3 71 SW_REVISION Register 7 6 5 4 3 2 1 0 SW_REVISION R X Table 3 78 SW_REVISION Register Field Descriptions Bit Field Type Reset Description 7 0 SW_REVISION R X Software SW revision register This revision will be representative of...

Page 87: ...HWRST Figure 3 72 PMU_SECONDARY_INT2 Register 7 6 5 4 3 2 1 0 RESERVED DVFS_INT_SR C RESERVED DVFS_MASK RC 0h RC 0h R 0h R W 0h Table 3 79 PMU_SECONDARY_INT2 Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED RC 0h 4 DVFS_INT_SRC RC 0h DVFS Voltage plus offset over voltage max interrupt status source 0 DVFS Voltage plus offset over voltage max is not the source of interrupt ...

Page 88: ...ed in Table 3 80 Return to Summary Table Configuration and status of the Boot Status Register The boot mode is only latched during POR and should not be changed while the PMIC is supplied RESET register domain POR Figure 3 73 BOOT_STATUS Register 7 6 5 4 3 2 1 0 RESERVED BOOT_MODE R 0h R X Table 3 80 BOOT_STATUS Register Field Descriptions Bit Field Type Reset Description 7 1 RESERVED R 0h 0 BOOT_...

Page 89: ...SSIGN2 NSLEEP input signal LDO resource assignment register 2 RESET register domain HWRST Section 3 8 6 1DEh ENABLE1_RES_ASSIGN ENABLE1 resource assignment register RESET register domain HWRST Section 3 8 7 1DFh ENABLE1_SMPS_ASSIGN ENABLE1 input signal SMPS resource assignment register RESET register domain HWRST Section 3 8 8 1E0h ENABLE1_LDO_ASSIGN1 ENABLE1 input signal LDO resource assignment r...

Page 90: ...n to Summary Table REGEN1 control register RESET register domain SWORST Figure 3 74 REGEN1_CTRL Register 7 6 5 4 3 2 1 0 RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R 0h R 0h R 0h R W 0h R 0h R W X Table 3 82 REGEN1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R 0h 4 STATUS R 0h REGEN1 Status 0 OFF 1 ON 3 RESERVED R 0h 2 MODE_SLEEP R W 0h REGEN1 SLEE...

Page 91: ...urn to Summary Table PLLEN control register RESET register domain SWORST Figure 3 75 PLLEN_CTRL Register 7 6 5 4 3 2 1 0 RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R 0h R 0h R 0h R W 0h R 0h R W 0h Table 3 83 PLLEN_CTRL Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R 0h 4 STATUS R 0h PLLEN Status 0 OFF 1 ON 3 RESERVED R 0h 2 MODE_SLEEP R W 0h PLLEN SLEEP ...

Page 92: ...ter domain HWRST Figure 3 76 NSLEEP_RES_ASSIGN Register 7 6 5 4 3 2 1 0 RESERVED PLL_EN REGEN3 REGEN2 REGEN1 R 0h R W 0h R W 0h R W 0h R W 0h Table 3 84 NSLEEP_RES_ASSIGN Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 PLL_EN R W 0h 0 NSLEEP has no effect on PLL_EN 1 PLL_EN is controlled by NSLEEP 2 REGEN3 R W 0h 0 NSLEEP has no effect on REGEN3 1 REGEN3 is control...

Page 93: ...D SMPS4 SMPS3 RESERVED SMPS2 SMPS1 R W 0h R W 0h R 0h R W 0h R W 0h R W 0h R W 0h R W 0h Table 3 85 NSLEEP_SMPS_ASSIGN Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R W 0h 6 SMPS5 R W 0h 0 NSLEEP has no effect on SMPS5 1 SMPS5 is controlled by NSLEEP 5 RESERVED R 0h 4 SMPS4 R W 0h 0 NSLEEP has no effect on SMPS4 1 SMPS4 is controlled by NSLEEP 3 SMPS3 R W 0h 0 NSLEEP has ...

Page 94: ...ET register domain HWRST Figure 3 78 NSLEEP_LDO_ASSIGN1 Register 7 6 5 4 3 2 1 0 LDO4 RESERVED RESERVED RESERVED RESERVED RESERVED LDO2 LDO1 R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h R W 0h Table 3 86 NSLEEP_LDO_ASSIGN1 Register Field Descriptions Bit Field Type Reset Description 7 LDO4 R W 0h 0 NSLEEP has no effect on LDO4 1 LDO4 is controlled by NSLEEP 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R...

Page 95: ...ource assignment register 2 RESET register domain HWRST Figure 3 79 NSLEEP_LDO_ASSIGN2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED LDO3 LDO5 RESERVED R 0h R 0h R 0h R 0h R 0h R W 0h R W 0h R 0h Table 3 87 NSLEEP_LDO_ASSIGN2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R 0h 3 RESERVED R 0h 2 LDO3 R ...

Page 96: ...domain HWRST Figure 3 80 ENABLE1_RES_ASSIGN Register 7 6 5 4 3 2 1 0 RESERVED PLL_EN REGEN3 REGEN2 REGEN1 R 0h R W 0h R W 0h R W 0h R W 0h Table 3 88 ENABLE1_RES_ASSIGN Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 PLL_EN R W 0h 0 ENABLE1 has no effect on PLL_EN 1 PLL_EN is controlled by ENABLE1 2 REGEN3 R W 0h 0 ENABLE1 has no effect on REGEN3 1 REGEN3 is contro...

Page 97: ...D SMPS4 SMPS3 RESERVED SMPS2 SMPS1 R 0h R W 0h R 0h R W 0h R W 0h R 0h R W 0h R W 0h Table 3 89 ENABLE1_SMPS_ASSIGN Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SMPS5 R W 0h 0 ENABLE1 has no effect on SMPS5 1 SMPS5 is controlled by ENABLE1 5 RESERVED R 0h 4 SMPS4 R W 0h 0 ENABLE1 has no effect on SMPS4 1 SMPS4 is controlled by ENABLE1 3 SMPS3 R W 0h 0 ENABLE1 has ...

Page 98: ...ET register domain HWRST Figure 3 82 ENABLE1_LDO_ASSIGN1 Register 7 6 5 4 3 2 1 0 LDO4 RESERVED RESERVED RESERVED RESERVED RESERVED LDO2 LDO1 R W 0h R 0h R 0h R 0h R 0h R 0h R W 0h R W 0h Table 3 90 ENABLE1_LDO_ASSIGN1 Register Field Descriptions Bit Field Type Reset Description 7 LDO4 R W 0h 0 ENABLE1 has no effect on LDO4 1 LDO4 is controlled by ENABLE1 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED...

Page 99: ...urce assignment register 2 RESET register domain HWRST Figure 3 83 ENABLE1_LDO_ASSIGN2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED LDO3 LDO5 RESERVED R 0h R 0h R 0h R 0h R 0h R W 0h R W 0h R 0h Table 3 91 ENABLE1_LDO_ASSIGN2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R 0h 3 RESERVED R 0h 2 LDO3 R...

Page 100: ... domain HWRST Figure 3 84 ENABLE2_RES_ASSIGN Register 7 6 5 4 3 2 1 0 RESERVED PLL_EN REGEN3 REGEN2 REGEN1 R 0h R W 0h R W 0h R W 0h R W 0h Table 3 92 ENABLE2_RES_ASSIGN Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 PLL_EN R W 0h 0 ENABLE2 has no effect on PLL_EN 1 PLL_EN is controlled by ENABLE2 2 REGEN3 R W 0h 0 ENABLE2 has no effect on REGEN3 1 REGEN3 is contr...

Page 101: ...ED SMPS4 SMPS3 RESERVED SMPS2 SMPS1 R 0h R W 0h R 0h R W 0h R W 0h R 0h R W 0h R W 0h Table 3 93 ENABLE2_SMPS_ASSIGN Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SMPS5 R W 0h 0 ENABLE2 has no effect on SMPS5 1 SMPS5 is controlled by ENABLE2 5 RESERVED R 0h 4 SMPS4 R W 0h 0 ENABLE2 has no effect on SMPS4 1 SMPS4 is controlled by ENABLE2 3 SMPS3 R W 0h 0 ENABLE2 has...

Page 102: ...T register domain HWRST Figure 3 86 ENABLE2_LDO_ASSIGN1 Register 7 6 5 4 3 2 1 0 LDO4 RESERVED RESERVED RESERVED RESERVED RESERVED LDO2 LDO1 R W 0h R 0h R 0h R 0h R W 0h R 0h R W 0h R W 0h Table 3 94 ENABLE2_LDO_ASSIGN1 Register Field Descriptions Bit Field Type Reset Description 7 LDO4 R W 0h 0 ENABLE2 has no effect on LDO4 1 LDO4 is controlled by ENABLE2 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVE...

Page 103: ...ource assignment register 2 RESET register domain HWRST Figure 3 87 ENABLE2_LDO_ASSIGN2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED LDO3 LDO5 RESERVED R 0h R 0h R 0h R 0h R 0h R W 0h R W 0h R 0h Table 3 95 ENABLE2_LDO_ASSIGN2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R 0h 3 RESERVED R 0h 2 LDO3 ...

Page 104: ...rn to Summary Table REGEN2 control register RESET register domain SWORST Figure 3 88 REGEN2_CTRL Register 7 6 5 4 3 2 1 0 RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R 0h R 0h R 0h R W 0h R 0h R W X Table 3 96 REGEN2_CTRL Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R 0h 4 STATUS R 0h REGEN2 Status 0 OFF 1 ON 3 RESERVED R 0h 2 MODE_SLEEP R W 0h REGEN2 SLE...

Page 105: ...rn to Summary Table REGEN3 control register RESET register domain SWORST Figure 3 89 REGEN3_CTRL Register 7 6 5 4 3 2 1 0 RESERVED STATUS RESERVED MODE_SLEEP RESERVED MODE_ACTIV E R 0h R 0h R 0h R W 0h R 0h R W X Table 3 97 REGEN3_CTRL Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R 0h 4 STATUS R 0h REGEN3 Status 0 OFF 1 ON 3 RESERVED R 0h 2 MODE_SLEEP R W 0h REGEN3 SLE...

Page 106: ...take care about the pull up pull down selections versus the IO direction and type Open drain Push Pull Section 3 9 3 1F6h PU_PD_INPUT_CTRL3 Pull up Pull down control register 3 RESET register domain HWRST Note It is user responsibility to take care about the pull up pull down selections versus the IO direction and type Open drain Push Pull Section 3 9 4 1F8h OD_OUTPUT_CTRL Open Drain control regis...

Page 107: ...pen Drain control register 2 RESET register domain HWRST Figure 3 90 OD_OUTPUT_CTRL2 Register 7 6 5 4 3 2 1 0 RESET_OUT_ OD RESERVED RESERVED REGEN2_OD RESERVED R W X R 0h R 0h R W X R 0h Table 3 99 OD_OUTPUT_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7 RESET_OUT_OD R W X 0 open drain not enable Push Pull enabled 1 open drain enable Push Pull not enable 6 3 RESERVED R 0h 2 ...

Page 108: ...he pull up pull down selections versus the IO direction and type Open drain Push Pull Figure 3 91 PU_PD_INPUT_CTRL1 Register 7 6 5 4 3 2 1 0 RESERVED RESET_IN_PD RESERVED RESERVED RESERVED PWRDOWN_P D RESERVED NRESWARM_ PD R 0h R W X R 0h R 0h R 0h R W X R 0h R W X Table 3 100 PU_PD_INPUT_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESET_IN_PD R W X 0 Pull ...

Page 109: ...he IO direction and type Open drain Push Pull Figure 3 92 PU_PD_INPUT_CTRL2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED ENABLE2_PD ENABLE1_PU ENABLE1_PD NSLEEP_PU NSLEEP_PD R 0h R 0h R W 1h R W 0h R W 1h R W 1h R W 0h Table 3 101 PU_PD_INPUT_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7 6 RESERVED R 0h 5 RESERVED R 0h 4 ENABLE2_PD R W 1h 0 Pull down not enabled 1 Pull down en...

Page 110: ...the pull up pull down selections versus the IO direction and type Open drain Push Pull Figure 3 93 PU_PD_INPUT_CTRL3 Register 7 6 5 4 3 2 1 0 RESERVED SYNCDCDC_P D RESERVED RESERVED RESERVED POWERHOLD_ PD RESERVED RESERVED R 0h R W 1h R 0h R 0h R 0h R W 1h R 0h R 0h Table 3 102 PU_PD_INPUT_CTRL3 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SYNCDCDC_PD R W 1h Secon...

Page 111: ...user responsibility to take care about the IO direction and type Open drain Push Pull versus the pull up pull down selections Figure 3 94 OD_OUTPUT_CTRL Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED INT_OD RESERVED RESERVED RESERVED R 0h R 0h R 0h R 0h R W 0h R 0h R 0h R 0h Table 3 103 OD_OUTPUT_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESE...

Page 112: ...ndary functions 0 inversion not enable active high default 1 inversion is enabled active low In case NSLEEP input line is selected as secondary function 0 Resources will go in SLEEP mode when NSLEEP is low default 1 Resources will go in SLEEP mode when NSLEEP is high 5 GPIO_5_POLARITY R W X Select the polarity of the GPIO_5 input or output lines and associated secondary functions 0 inversion not e...

Page 113: ...s switch off when RESET_IN is low default 1 Device is switch off when RESET_IN is high In case NRESWARM input line is selected as secondary function 0 Device is warm reset when NRESWARM is low default 1 Device is warm reset when NRESWARM is high 0 GPIO_0_POLARITY R W X Select the polarity of the GPIO_0 input or output lines and associated secondary functions 0 inversion not enable active high defa...

Page 114: ...3 pin pad 00 Primary function is selected GPIO_3 01 Secondary function is selected ENABLE2 10 Secondary function is selected REGEN1 11 Secondary function is selected SYNCDCDC 5 4 GPIO_2 R W X Selection primary or secondary function associated to GPIO_2 pin pad 00 Primary function is selected GPIO_2 01 Reserved 10 Secondary function is selected ENABLE1 11 Secondary function is selected I2C_SDA_SDO ...

Page 115: ...cts the primary or secondary function associated to the SYNCCLKOUT pin pad 0 Primary function is selected SYNCDCDCCLK 1 Secondary function is selected CLK32KGO 5 4 GPIO_6 R W X Selection primary or secondary function associated to GPIO_6 pin pad 00 Primary function is selected GPIO_6 01 Secondary function is selected NSLEEP 10 Secondary function is selected POWERGOOD 11 Secondary function is selec...

Page 116: ... Description 7 I2C2OTP_EN R W 0h I2C to OTP I2C2OTP feature selection EVM purpose only 0 I2C2OTP is disable 1 I2C2OTP is enabled 6 I2C2OTP_PAGESEL R W 0h I2C to OTP I2C2OTP page selection EVM purpose only 0 page0 is selected OTP page0 Test Trim reserved OTP page1 Sequencer LSB OTP page2 Sequencer OTP page3 Sequencer 1 page1 is selected OTP page4 Sequencer MSB OTP page5 Config 5 ID_I2C2 R W X I2C_2...

Page 117: ...gister 2 RESET register domain HWRST Section 3 10 5 217h INT2_LINE_STATE Interrupt source line state Register 2 RESET register domain HWRST Section 3 10 6 21Ah INT3_STATUS Interrupt Status Register 3 The bit can be cleared on read or cleared by writing 1 see INT_CTRL INT_CLEAR RESET register domain HWRST Section 3 10 7 21Bh INT3_MASK Interrupt Line Mask Register 3 RESET register domain HWRST Secti...

Page 118: ...RESERVED RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h Table 3 109 INT1_STATUS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED RC 0h 6 VSYS_MON RC 0h VSYS_MON status bit register internal event 0 no detection 1 Rising or Falling edge are detected 5 HOTDIE RC 0h HOTDIE status bit register internal event 0 no detection 1 Rising or Falling edge are detected 4 PWRDOWN RC 0h P...

Page 119: ...t register 0 VSYS_MON line is enabled An interrupt is generated on INT line 1 VSYS_MON line is masked No interrupt is generated on INT line 5 HOTDIE R W X HOTDIE Line Mask bit register 0 HOTDIE line is enabled An interrupt is generated on INT line 1 HOTDIE line is masked No interrupt is generated on INT line 4 PWRDOWN R W X PWRDOWN Line Mask bit register 0 PWRDOWN line is enabled An interrupt is g...

Page 120: ...ON RESERVED R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h Table 3 111 INT1_LINE_STATE Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 VSYS_MON R 0h VSYS_MON line state register 0 VSYS_MON line is equal to 0 1 VSYS_MON line is equal to 1 5 HOTDIE R 0h HOTDIE line state register 0 HOTDIE line is equal to 0 1 HOTDIE line is equal to 1 4 PWRDOWN R 0h PWRDOWN line state registe...

Page 121: ...C 0h RC 0h Table 3 112 INT2_STATUS Register Field Descriptions Bit Field Type Reset Description 7 RESERVED RC 0h 6 SHORT RC 0h SHORT status bit register associated internal event 0 no detection 1 Rising or falling edge are detected 5 FSD RC 0h First Supply Detection FSD status bit register internal event 0 no detection 1 Rising edge is detected To know the interrupt source FSD First Supply Detecti...

Page 122: ...ORT line is enabled An interrupt is generated on INT line 1 SHORT line is masked No interrupt is generated on INT line 5 FSD R W X First Supply Detection FSD Line Mask bit register 0 FSD line is enabled An interrupt is generated on INT line 1 FSD line is masked No interrupt is generated on INT line 4 RESET_IN R W X RESET_IN Line Mask bit register 0 RESET_IN line is enabled An interrupt is generate...

Page 123: ...R 0h R 0h Table 3 114 INT2_LINE_STATE Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 SHORT R 0h SHORT line state register 0 SHORT line is equal to 0 1 SHORT line is equal to 1 5 FSD R 0h First Supply Detection FSD line state register 0 FSD line is equal to 0 1 FSD line is equal to 1 4 RESET_IN R 0h RESET_IN line state register 0 RESET_IN line is equal to 0 1 RESET_I...

Page 124: ...ESERVED RESERVED RESERVED GPADC_EOC_ SW GPADC_AUTO _1 GPADC_AUTO _0 RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h RC 0h Table 3 115 INT3_STATUS Register Field Descriptions Bit Field Type Reset Description 7 VBUS RC 0h VBUS status bit register VBUS pin 0 no detection 1 Rising or falling edge are detected 6 RESERVED RC 0h 5 RESERVED RC 0h 4 RESERVED RC 0h 3 RESERVED RC 0h 2 GPADC_EOC_SW RC 0h GPADC_EOC_...

Page 125: ...VBUS Line Mask bit register VBUS pin 0 VBUS line is enabled An interrupt is generated on INT line 1 VBUS line is masked No interrupt is generated on INT line 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R 0h 3 RESERVED R 0h 2 GPADC_EOC_SW R W X GPADC_EOC_SW Line Mask bit register Internal event 0 GPADC_EOC_SW line is enabled An interrupt is generated on INT line 1 GPADC_EOC_SW line is masked No inte...

Page 126: ... _1 GPADC_AUTO _0 R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h Table 3 117 INT3_LINE_STATE Register Field Descriptions Bit Field Type Reset Description 7 VBUS R 0h VBUS line state register VBUS pin 0 VBUS line is equal to 0 1 VBUS line is equal to 1 6 RESERVED R 0h 5 RESERVED R 0h 4 RESERVED R 0h 3 RESERVED R 0h 2 GPADC_EOC_SW R 0h GPADC_EOC_SW line state register Internal event 0 GPADC_EOC_SW line is ...

Page 127: ...pe Reset Description 7 RESERVED RC 0h 6 GPIO_6 RC 0h GPIO_6 status bit register associated to GPIO_6 pin 0 no detection 1 Rising or Falling edge are detected 5 GPIO_5 RC 0h GPIO_5 status bit register associated to GPIO_5 pin 0 no detection 1 Rising or Falling edge are detected 4 GPIO_4 RC 0h GPIO_4 status bit register associated to GPIO_4 pin 0 no detection 1 Rising or Falling edge are detected 3 ...

Page 128: ...enabled An interrupt is generated on INT line 1 GPIO_5 line is masked No interrupt is generated on INT line 4 GPIO_4 R W X GPIO_4 Line Mask bit register 0 GPIO_4 line is enabled An interrupt is generated on INT line 1 GPIO_4 line is masked No interrupt is generated on INT line Note Cannot be used as wake up event because buffer needs power supply So must be masked by default OTP 3 GPIO_3 R W X GPI...

Page 129: ..._LINE_STATE Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6 R 0h GPIO_6 line state register 0 GPIO_6 line is equal to 0 1 GPIO_6 line is equal to 1 5 GPIO_5 R 0h GPIO_5 line state register 0 GPIO_5 line is equal to 0 1 GPIO_5 line is equal to 1 4 GPIO_4 R 0h GPIO_4 line state register 0 GPIO_4 line is equal to 0 1 GPIO_4 line is equal to 1 3 GPIO_3 R 0h GPIO_3...

Page 130: ...TECT1 Register Field Descriptions Bit Field Type Reset Description 7 GPIO_3_RISING R W 1h 0 Rising edge detection not enabled 1 Rising edge detection enable default 6 GPIO_3_FALLING R W 1h 0 Falling edge detection not enabled 1 Falling edge detection enable default 5 GPIO_2_RISING R W 1h 0 Rising edge detection not enabled 1 Rising edge detection enable default 4 GPIO_2_FALLING R W 1h 0 Falling ed...

Page 131: ... 0h R 0h R W 1h R W 1h R W 1h R W 1h R W 1h R W 1h Table 3 122 INT4_EDGE_DETECT2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 GPIO_6_RISING R W 1h 0 Rising edge detection not enabled 1 Rising edge detection enable default 4 GPIO_6_FALLING R W 1h 0 Falling edge detection not enabled 1 Falling edge detection enable default 3 GPIO_5_RISING R W 1h 0 Ri...

Page 132: ...TRL Register 7 6 5 4 3 2 1 0 RESERVED INT_PENDING RESERVED INT_CLEAR R 0h R W 0h R 0h R W 0h Table 3 123 INT_CTRL Register Field Descriptions Bit Field Type Reset Description 7 3 RESERVED R 0h 2 INT_PENDING R W 0h Pending interrupt latching feature selection interrupt latched in case of new event before clearing on same line 0 Enabled default 1 Not enabled 1 RESERVED R 0h 0 INT_CLEAR R W 0h Select...

Page 133: ... Register 7 6 5 4 3 2 1 0 RESERVED CRC_FORCE_ OFF CRC_RESULT S_CFG CRC_RESULT S_SEQ CRC_RESULT S_TRIM R 0h R 0h R 0h R 0h R 0h Table 3 124 OTP_CRC_RESULTS Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 CRC_FORCE_OFF R 0h 0 Power Sequence is executed through the end after OTP CRC Check 1 Power Sequence is forced off after OTP CRC Check 2 CRC_RESULTS_CFG R 0h CRC re...

Page 134: ... 3 125 should be considered as reserved locations and the register contents should not be modified Table 3 125 FUNC_ID Registers Address Acronym Register Name Section 24Fh VENDOR_ID_LSB Vendor ID Register LSB RESET register domain HWRST Section 3 11 1 250h VENDOR_ID_MSB Vendor ID Register MSB RESET register domain HWRST Section 3 11 2 251h PRODUCT_ID_LSB Product ID Register LSB RESET register doma...

Page 135: ...ter Address 24Fh reset 51h VENDOR_ID_LSB is shown in Figure 3 115 and described in Table 3 126 Return to Summary Table Vendor ID Register LSB RESET register domain HWRST Figure 3 115 VENDOR_ID_LSB Register 7 6 5 4 3 2 1 0 VENDOR_ID R 51h Table 3 126 VENDOR_ID_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 VENDOR_ID R 51h Texas Instruments USB Vendor ID 8 LSBs Default value 0x...

Page 136: ...ster Address 250h reset 4h VENDOR_ID_MSB is shown in Figure 3 116 and described in Table 3 127 Return to Summary Table Vendor ID Register MSB RESET register domain HWRST Figure 3 116 VENDOR_ID_MSB Register 7 6 5 4 3 2 1 0 VENDOR_ID R 4h Table 3 127 VENDOR_ID_MSB Register Field Descriptions Bit Field Type Reset Description 7 0 VENDOR_ID R 4h Texas Instruments USB Vendor ID 8 MSBs Default value 0x04...

Page 137: ...er Address 251h reset 17h PRODUCT_ID_LSB is shown in Figure 3 117 and described in Table 3 128 Return to Summary Table Product ID Register LSB RESET register domain HWRST Figure 3 117 PRODUCT_ID_LSB Register 7 6 5 4 3 2 1 0 PRODUCT_ID R 17h Table 3 128 PRODUCT_ID_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 PRODUCT_ID R 17h Texas Instruments Product ID 8 LSBs Default value ...

Page 138: ...ter Address 252h reset 9h PRODUCT_ID_MSB is shown in Figure 3 118 and described in Table 3 129 Return to Summary Table Product ID Register MSB RESET register domain HWRST Figure 3 118 PRODUCT_ID_MSB Register 7 6 5 4 3 2 1 0 PRODUCT_ID R 9h Table 3 129 PRODUCT_ID_MSB Register Field Descriptions Bit Field Type Reset Description 7 0 PRODUCT_ID R 9h Texas Instruments Product ID 8 MSBs Default value 0x...

Page 139: ...unce enable register 1 RESET register domain HWRST Section 3 12 4 284h GPIO_CLEAR_DATA_OUT GPIO Clear Data Out Register 1 RESET register domain HWRST Section 3 12 5 285h GPIO_SET_DATA_OUT GPIO Set Data Out Register 1 RESET register domain HWRST Section 3 12 6 286h PU_PD_GPIO_CTRL1 Pull up Pull down control register 1 RESET register domain HWRST Note It is user responsibility to take care about the...

Page 140: ...IN Register 7 6 5 4 3 2 1 0 RESERVED GPIO_6_IN GPIO_5_IN GPIO_4_IN GPIO_3_IN GPIO_2_IN GPIO_1_IN GPIO_0_IN R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h Table 3 131 GPIO_DATA_IN Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6_IN R 0h Data read value in of the GPIO_6 5 GPIO_5_IN R 0h Data read value in of the GPIO_5 4 GPIO_4_IN R 0h Data read value in of the GPIO_4 3...

Page 141: ...W 0h Table 3 132 GPIO_DATA_DIR Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6_DIR R W 0h 0 buffer in input configuration default 1 buffer in output configuration 5 GPIO_5_DIR R W 0h 0 buffer in input configuration default 1 buffer in output configuration 4 GPIO_4_DIR R W 0h 0 buffer in input configuration default 1 buffer in output configuration 3 GPIO_3_DIR ...

Page 142: ... RESERVED GPIO_6_OUT GPIO_5_OUT GPIO_4_OUT GPIO_3_OUT GPIO_2_OUT GPIO_1_OUT GPIO_0_OUT R 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h Table 3 133 GPIO_DATA_OUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6_OUT R W 0h Data write value out of the GPIO_6 5 GPIO_5_OUT R W 0h Data write value out of the GPIO_5 4 GPIO_4_OUT R W 0h Data write value out of th...

Page 143: ...3_DEBO UNCE_EN GPIO_2_DEBO UNCE_EN GPIO_1_DEBO UNCE_EN GPIO_0_DEBO UNCE_EN R 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h Table 3 134 GPIO_DEBOUNCE_EN Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6_DEBOUNCE_EN R W 0h 0 No debounce default 1 Debounce enabled 5 GPIO_5_DEBOUNCE_EN R W 0h 0 No debounce default 1 Debounce enabled 4 GPIO_4_DEBOUNCE_EN R W 0h...

Page 144: ..._OUT GPIO_2_CLEA R_DATA_OUT GPIO_1_CLEA R_DATA_OUT GPIO_0_CLEA R_DATA_OUT R 0h W 0h W 0h W 0h W 0h W 0h W 0h W 0h Table 3 135 GPIO_CLEAR_DATA_OUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6_CLEAR_DATA_ OUT W 0h 0 no action on GPIO_6 bit 1 CLEAR GPIO_6 bit 5 GPIO_5_CLEAR_DATA_ OUT W 0h 0 no action on GPIO_5 bit 1 CLEAR GPIO_5 bit 4 GPIO_4_CLEAR_DATA_ OUT W ...

Page 145: ..._SET_ DATA_OUT GPIO_2_SET_ DATA_OUT GPIO_1_SET_ DATA_OUT GPIO_0_SET_ DATA_OUT R 0h W 0h W 0h W 0h W 0h W 0h W 0h W 0h Table 3 136 GPIO_SET_DATA_OUT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_6_SET_DATA_OU T W 0h 0 no action on GPIO_6 bit 1 SET GPIO_6 bit 5 GPIO_5_SET_DATA_OU T W 0h 0 no action on GPIO_5 bit 1 SET GPIO_5 bit 4 GPIO_4_SET_DATA_OU T W 0h 0 no ...

Page 146: ...tion and type Open drain Push Pull Figure 3 125 PU_PD_GPIO_CTRL1 Register 7 6 5 4 3 2 1 0 RESERVED GPIO_3_PD GPIO_2_PU GPIO_2_PD RESERVED GPIO_1_PD RESERVED GPIO_0_PD R 0h R W X R W X R W X R 0h R W X R 0h R W X Table 3 137 PU_PD_GPIO_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 GPIO_3_PD R W X 0 Pull down not enabled 1 Pull down enabled default 5 GPIO_2_PU ...

Page 147: ...ctions versus the GPIO direction and type Open drain Push Pull Figure 3 126 PU_PD_GPIO_CTRL2 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED GPIO_6_PD RESERVED GPIO_5_PD GPIO_4_PU GPIO_4_PD R 0h R 0h R 0h R W X R 0h R W X R W X R W X Table 3 138 PU_PD_GPIO_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 GPIO_6_PD R W X 0 Pull...

Page 148: ...tion and type Open drain Push Pull versus the pull up pull down selections Figure 3 127 OD_OUTPUT_GPIO_CTRL Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED GPIO_4_OD RESERVED GPIO_2_OD RESERVED RESERVED R 0h R 0h R 0h R W X R 0h R W X R 0h R 0h Table 3 139 OD_OUTPUT_GPIO_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 RESERVED R 0h 4 GPIO_4_O...

Page 149: ...mended to put the lower channel to convert in AUTO_CONV0_SEL and the higher channel to convert in AUTO_CONV0_SEL Section 3 13 7 2C9h GPADC_AUTO_CONV0_LSB GPADC data results of the Automatic Periodic conversion 0 LSB RESET register domain HWRST Section 3 13 8 2CAh GPADC_AUTO_CONV0_MSB GPADC data results of the Automatic Periodic conversion 0 MSB RESET register domain HWRST Section 3 13 9 2CBh GPADC...

Page 150: ...ister Descriptions Table 3 140 FUNC_GPADC Registers continued Address Acronym Register Name Section 2D4h GPADC_SMPS_ILMONITOR_EN GPADC SMPS selection for current measurement RESET register domain HWRST Section 3 13 19 2D5h GPADC_SMPS_VSEL_MONITORING GPADC SMPS voltage monitoring related to ILMONITORING measurement RESET register domain HWRST Section 3 13 20 ...

Page 151: ...egister RESET register domain HWRST Figure 3 128 GPADC_CTRL1 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED GPADC_FORC E R 0h R 0h R 0h R 0h R 0h R W 0h Table 3 141 GPADC_CTRL1 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 RESERVED R 0h 5 4 RESERVED R 0h 3 2 RESERVED R 0h 1 RESERVED R 0h 0 GPADC_FORCE R W 0h Force GPADC module to active Alway...

Page 152: ...ummary Table GPADC FLUSH register RESET register domain HWRST Figure 3 129 GPADC_FLUSH Register 7 6 5 4 3 2 1 0 RESERVED EXTEND_DEL AY FLUSH R 0h R W 0h R W 0h Table 3 142 GPADC_FLUSH Register Field Descriptions Bit Field Type Reset Description 7 2 RESERVED R 0h 1 EXTEND_DELAY R W 0h Extend delay before SW conversion 0 0 µs default 1 450 µs 0 FLUSH R W 0h Flush the conversion result of the GPADC w...

Page 153: ...ption 7 SHUTDOWN_CONV1 R W 0h Shut down control based on Auto conversions only for CONV1 0 shut down not enabled default 1 enable shut down of the platform if interrupt is not clear within delay time 6 SHUTDOWN_CONV0 R W 0h Shut down control based on Auto conversions only for CONV0 0 shut down not enabled default 1 enable shut down of the platform if interrupt is not clear within delay time 5 AUTO...

Page 154: ... and described in Table 3 144 Return to Summary Table GPADC Status Register RESET register domain HWRST Figure 3 131 GPADC_STATUS Register 7 6 5 4 3 2 1 0 RESERVED GPADC_AVAIL ABLE RESERVED R 0h R 1h R 0h Table 3 144 GPADC_STATUS Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R 0h 4 GPADC_AVAILABLE R 1h GPADC availability status 0 Conversions not completed GPADC not avai...

Page 155: ... 132 and described in Table 3 145 Return to Summary Table GPADC FLSUH Enable register RESET register domain HWRST Figure 3 132 GPADC_FLUSH_EN Register 7 6 5 4 3 2 1 0 FLUSH_EN RESERVED RESERVED R W 0h R 0h R W 0h Table 3 145 GPADC_FLUSH_EN Register Field Descriptions Bit Field Type Reset Description 7 FLUSH_EN R W 0h GPADC Flush Enable 0 The Flush operation of GPADC is locked default 1 The Flush o...

Page 156: ...escribed in Table 3 146 Return to Summary Table GPADC stuck status RESET register domain HWRST Figure 3 133 GPADC_STUCK Register 7 6 5 4 3 2 1 0 RESERVED STUCK RESERVED R 0h R 0h R 0h Table 3 146 GPADC_STUCK Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R 0h 4 STUCK R 0h GPADC stuck status 0 GPADC is not stuck in a busy state 1 GPADC is stuck in a busy state Flushing th...

Page 157: ...PADC_AUTO_CONV0 register and the second one is placed in GPADC_AUTO_CONV0 register It is why it is recommended to put the lower channel to convert in AUTO_CONV0_SEL and the higher channel to convert in AUTO_CONV0_SEL Figure 3 134 GPADC_AUTO_SELECT Register 7 6 5 4 3 2 1 0 AUTO_CONV1_SEL AUTO_CONV0_SEL R W 0h R W 0h Table 3 147 GPADC_AUTO_SELECT Register Field Descriptions Bit Field Type Reset Desc...

Page 158: ...set 0h GPADC_AUTO_CONV0_LSB is shown in Figure 3 135 and described in Table 3 148 Return to Summary Table GPADC data results of the Automatic Periodic conversion 0 LSB RESET register domain HWRST Figure 3 135 GPADC_AUTO_CONV0_LSB Register 7 6 5 4 3 2 1 0 AUTO_CONV0_LSB R 0h Table 3 148 GPADC_AUTO_CONV0_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 AUTO_CONV0_LSB R 0h AUTO Co...

Page 159: ...O_CONV0_MSB is shown in Figure 3 136 and described in Table 3 149 Return to Summary Table GPADC data results of the Automatic Periodic conversion 0 MSB RESET register domain HWRST Figure 3 136 GPADC_AUTO_CONV0_MSB Register 7 6 5 4 3 2 1 0 RESERVED AUTO_CONV0_MSB R 0h R 0h Table 3 149 GPADC_AUTO_CONV0_MSB Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 0 AUTO_CONV0_...

Page 160: ...eset 0h GPADC_AUTO_CONV1_LSB is shown in Figure 3 137 and described in Table 3 150 Return to Summary Table GPADC data results of the Automatic Periodic conversion 1 LSB RESET register domain HWRST Figure 3 137 GPADC_AUTO_CONV1_LSB Register 7 6 5 4 3 2 1 0 AUTO_CONV1_LSB R 0h Table 3 150 GPADC_AUTO_CONV1_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 AUTO_CONV1_LSB R 0h AUTO C...

Page 161: ...O_CONV1_MSB is shown in Figure 3 138 and described in Table 3 151 Return to Summary Table GPADC data results of the Automatic Periodic conversion 1 MSB RESET register domain HWRST Figure 3 138 GPADC_AUTO_CONV1_MSB Register 7 6 5 4 3 2 1 0 RESERVED AUTO_CONV1_MSB R 0h R 0h Table 3 151 GPADC_AUTO_CONV1_MSB Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 0 AUTO_CONV1_...

Page 162: ... 1 0 SW_CONV_EN RESERVED SW_START_C ONV0 SW_CONV0_SEL R W 0h R 0h R W 0h R W 0h Table 3 152 GPADC_SW_SELECT Register Field Descriptions Bit Field Type Reset Description 7 SW_CONV_EN R W 0h Software Conversion enabling 0 Software Conversion is not enable defaults 1 Software Conversion is enabled 6 5 RESERVED R 0h 4 SW_START_CONV0 R W 0h Toggle bit used by host processor to start a conversion Conver...

Page 163: ...ess 2CEh reset 0h GPADC_SW_CONV0_LSB is shown in Figure 3 140 and described in Table 3 153 Return to Summary Table GPADC data results of the Software conversion 0 LSB RESET register domain HWRST Figure 3 140 GPADC_SW_CONV0_LSB Register 7 6 5 4 3 2 1 0 SW_CONV0_LSB R 0h Table 3 153 GPADC_SW_CONV0_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 SW_CONV0_LSB R 0h SW Conversion 0 ...

Page 164: ... GPADC_SW_CONV0_MSB is shown in Figure 3 141 and described in Table 3 154 Return to Summary Table GPADC data results of the Software conversion 0 MSB RESET register domain HWRST Figure 3 141 GPADC_SW_CONV0_MSB Register 7 6 5 4 3 2 1 0 RESERVED SW_CONV0_MSB R 0h R 0h Table 3 154 GPADC_SW_CONV0_MSB Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 0 SW_CONV0_MSB R 0h S...

Page 165: ...ADC_THRES_CONV0_LSB is shown in Figure 3 142 and described in Table 3 155 Return to Summary Table LSB of Threshold reference to be compared to the Conversion 0 results RESET register domain HWRST Figure 3 142 GPADC_THRES_CONV0_LSB Register 7 6 5 4 3 2 1 0 THRES_CONV0_LSB R W 0h Table 3 155 GPADC_THRES_CONV0_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 THRES_CONV0_LSB R W 0h...

Page 166: ...ence to be compared to the Conversion 0 results RESET register domain HWRST Figure 3 143 GPADC_THRES_CONV0_MSB Register 7 6 5 4 3 2 1 0 THRES_CONV 0_POL RESERVED THRES_CONV0_MSB R W 0h R 0h R W 0h Table 3 156 GPADC_THRES_CONV0_MSB Register Field Descriptions Bit Field Type Reset Description 7 THRES_CONV0_POL R W 0h Threshold conversion 0 polarity 0 Interrupt generated if Conversion0 result is abov...

Page 167: ...ADC_THRES_CONV1_LSB is shown in Figure 3 144 and described in Table 3 157 Return to Summary Table LSB of Threshold reference to be compared to the Conversion 1 results RESET register domain HWRST Figure 3 144 GPADC_THRES_CONV1_LSB Register 7 6 5 4 3 2 1 0 THRES_CONV1_LSB R W 0h Table 3 157 GPADC_THRES_CONV1_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 THRES_CONV1_LSB R W 0h...

Page 168: ...ence to be compared to the Conversion 1 results RESET register domain HWRST Figure 3 145 GPADC_THRES_CONV1_MSB Register 7 6 5 4 3 2 1 0 THRES_CONV 1_POL RESERVED THRES_CONV1_MSB R W 0h R 0h R W 0h Table 3 158 GPADC_THRES_CONV1_MSB Register Field Descriptions Bit Field Type Reset Description 7 THRES_CONV1_POL R W 0h Threshold conversion 1 polarity 0 Interrupt generated if Conversion0 result is abov...

Page 169: ...RESERVED R 0h 6 SMPS_COMPMODE R W 0h ILMON comparator enable This bit can be written 1 ONLY if SMPS_ILMON_EN bit is already 1 If SMPS_ILMON_EN is written with 0 ILMON_COMPMODE bit will be automatically written with 0 too 0b ILMON Comparator is disabled 1b ILMON Comparator is enabled 5 SMPS_ILMON_EN R W 0h Selection of GPADC ILMONITOR feature 0b Feature not enabled default 1b Feature is enabled 4 S...

Page 170: ...rn to Summary Table GPADC SMPS voltage monitoring related to ILMONITORING measurement RESET register domain HWRST Figure 3 147 GPADC_SMPS_VSEL_MONITORING Register 7 6 5 4 3 2 1 0 ACTIVE_PHAS E SMPS_VSEL_MONITORING R 0h R 0h Table 3 160 GPADC_SMPS_VSEL_MONITORING Register Field Descriptions Bit Field Type Reset Description 7 ACTIVE_PHASE R 0h Specify the number of active phases during measurements ...

Page 171: ...IGNREV Registers Table 3 161 lists the memory mapped registers for the FUNC_DESIGNREV All register offset addresses not listed in Table 3 161 should be considered as reserved locations and the register contents should not be modified Table 3 161 FUNC_DESIGNREV Registers Address Acronym Register Name Section 357h DESIGNREV Silicon version number register RESET register domain POR Section 3 14 1 ...

Page 172: ...GNREV is shown in Figure 3 148 and described in Table 3 162 Return to Summary Table Silicon version number register RESET register domain POR Figure 3 148 DESIGNREV Register 7 6 5 4 3 2 1 0 RESERVED DESIGNREV R 0h R X Table 3 162 DESIGNREV Register Field Descriptions Bit Field Type Reset Description 7 4 RESERVED R 0h 3 0 DESIGNREV R X Value depending on silicon version number From metal bits 0000 ...

Page 173: ... Table 3 163 should be considered as reserved locations and the register contents should not be modified Table 3 163 FUNC_TRIM_GPADC Registers Address Acronym Register Name Section 3CDh GPADC_TRIM1 RESET register domain POR Section 3 15 1 3CEh GPADC_TRIM2 RESET register domain POR Section 3 15 2 3CFh GPADC_TRIM3 RESET register domain POR Section 3 15 3 3D0h GPADC_TRIM4 RESET register domain POR Se...

Page 174: ...49 and described in Table 3 164 Return to Summary Table RESET register domain POR Figure 3 149 GPADC_TRIM1 Register 7 6 5 4 3 2 1 0 GPADC_IN0_IN1_D1 GPADC_IN0_I N1_D1_SIGN R W 0h R W 0h Table 3 164 GPADC_TRIM1 Register Field Descriptions Bit Field Type Reset Description 7 1 GPADC_IN0_IN1_D1 R W 0h GPADC Input Channels 0 and 1 Calibration Value D1 0 GPADC_IN0_IN1_D1_SI GN R W 0h Sign bit of the GPA...

Page 175: ...50 and described in Table 3 165 Return to Summary Table RESET register domain POR Figure 3 150 GPADC_TRIM2 Register 7 6 5 4 3 2 1 0 GPADC_IN0_IN1_D2 GPADC_IN0_I N1_D2_SIGN R W 0h R W 0h Table 3 165 GPADC_TRIM2 Register Field Descriptions Bit Field Type Reset Description 7 1 GPADC_IN0_IN1_D2 R W 0h GPADC Input Channels 0 and 1 Calibration Value D2 0 GPADC_IN0_IN1_D2_SI GN R W 0h Sign bit of the GPA...

Page 176: ...re 3 151 and described in Table 3 166 Return to Summary Table RESET register domain POR Figure 3 151 GPADC_TRIM3 Register 7 6 5 4 3 2 1 0 VCC_D1 VCC_D1_SIGN R W 0h R W 0h Table 3 166 GPADC_TRIM3 Register Field Descriptions Bit Field Type Reset Description 7 1 VCC_D1 R W 0h GPADC Input Channel 3 Calibration Value D1 when HIGH_VCC_SENSE 0 0 VCC_D1_SIGN R W 0h Sign bit of the GPADC Input Channel 3 Ca...

Page 177: ...re 3 152 and described in Table 3 167 Return to Summary Table RESET register domain POR Figure 3 152 GPADC_TRIM4 Register 7 6 5 4 3 2 1 0 VCC_D2 VCC_D2_SIGN R W 0h R W 0h Table 3 167 GPADC_TRIM4 Register Field Descriptions Bit Field Type Reset Description 7 1 VCC_D2 R W 0h GPADC Input Channel 3 Calibration Value D2 when HIGH_VCC_SENSE 0 0 VCC_D2_SIGN R W 0h Sign bit of the GPADC Input Channel 3 Ca...

Page 178: ...re 3 153 and described in Table 3 168 Return to Summary Table RESET register domain POR Figure 3 153 GPADC_TRIM5 Register 7 6 5 4 3 2 1 0 VCC_D1 VCC_D1_SIGN R W 0h R W 0h Table 3 168 GPADC_TRIM5 Register Field Descriptions Bit Field Type Reset Description 7 1 VCC_D1 R W 0h GPADC Input Channel 3 Calibration Value D1 when HIGH_VCC_SENSE 1 0 VCC_D1_SIGN R W 0h Sign bit of the GPADC Input Channel 3 Ca...

Page 179: ...re 3 154 and described in Table 3 169 Return to Summary Table RESET register domain POR Figure 3 154 GPADC_TRIM6 Register 7 6 5 4 3 2 1 0 VCC_D2 VCC_D2_SIGN R W 0h R W 0h Table 3 169 GPADC_TRIM6 Register Field Descriptions Bit Field Type Reset Description 7 1 VCC_D2 R W 0h GPADC Input Channel 3 Calibration Value D2 when HIGH_VCC_SENSE 1 0 VCC_D2_SIGN R W 0h Sign bit of the GPADC Input Channel 3 Ca...

Page 180: ... the current version Changes from B Revision March 2017 to C Revision Page Changed the GPADC_FLUSH Register 152 Changes from A Revision September 2016 to B Revision Page First public release of document 2 Changes from Original June 2015 to A Revision Page Deleted the TPS65916 part number from the document 2 Updated GPADC_TRIM3 and GPADC_TRIM4 registers to HIGH_VCC_SENSE 0 3 Added the GPADC_TRIM5 a...

Page 181: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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