eUSCI_B SPI Registers
Table 19-12. UCBxCTLW0 Register Description (continued)
Bit
Field
Type
Reset
Description
0
UCSWRST
RW
1h
Software reset enable
0b = Disabled. eUSCI reset released for operation.
1b = Enabled. eUSCI logic held in reset state.
526
Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode
SLAU272C – May 2011 – Revised November 2013
Copyright © 2011–2013, Texas Instruments Incorporated