71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 25 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
M1
M0
Mode
Function
0
0
Mode 0
13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1 are held at zero.
0
1
Mode 1
16-bit Counter/Timer.
1
0
Mode2
8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,
while TL0 or TL1 is incremented every machine cycle. When TL(x)
overflows, a value from TH(x) is copied to TL(x).
1
1
Mode3
If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0
bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.
Table 19: Timers/Counters Mode Description
Note:
TL0 is affected by TR0 and gate control bits, and sets TF0 flag on overflow.
TH0 is affected by TR1 bit, and sets TF1 flag on overflow.
Timer/Counter Control Register (TCON)
MSB
LSB
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Table 20: The TCON Register
Bit
Symbol
Function
TCON.7 TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
TCON.6
TR1
Timer 1 Run control bit. If cleared, Timer 1 stops.
TCON.5 TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is processed.
TCON.4
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON.3 IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external pin
int1 is observed. Cleared when an interrupt is processed.
TCON.2 IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input
pin to cause an interrupt.
TCON.1 IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin
int0 is observed. Cleared when an interrupt is processed.
TCON.0 IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input
pin to cause interrupt.
Table 21: The TCON Register Bit Functions
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