71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 44 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
FUNCTIONAL DESCRIPTION
System Timing Summary
Figure 9 summarizes the timing relationships between the input MUX states. In this example,
MUX_DIV
=0 (six mux states) and
FIR_LEN
= 0 (2 PLLOUT cycles). Since FIR filter conversions require two or three PLLOUT cycles, the duration of each MUX
cycle is 1 + 2 * states defined by
MUX_DIV
if
FIR_LEN
= 0, and 1 + 3 * states defined by
MUX_DIV
if
FIR_LEN
= 1. Followed by
the conversions is a single PLLOUT cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the same
number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE
code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into DRAM is
shown in Figure 9.
Figure 9 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
PLLOUT
MUX STATE
0
MUX_DIV
Conversions (
MUX_DIV
=4 is shown)
Settle
ADC MUX Frame
ADC EXECUTION
S
MUX_SYNC
S
CE_EXECUTION
MAX CK COUNT
0
450
150
900
1350
1800
ADC0
ADC1
ADC2
ADC3
CK COUNT = CE_ floor((CE_ 2) / 5)
ADC, CE and SERIAL TIMING
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK COUNTS IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
.
ADC TIMING
CE TIMING
1
2
3
Figure 9: Timing Relationship between ADC MUX, CE, and Serial Transfers
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