71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 13 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Real-Time Monitor
The CE contains a Real Time Monitor (RTM), which can be programmed to monitor four selectable CE RAM locations at full
sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the
beginning of each CE code pass (see the Test Ports Section for details)
Power Up Short Circuit Detection Time
The 71M6403 detects a short circuit condition within less than 5 msec. (T2) after application of its power and a stable reference
clock. This delay includes the firmware startup time for both the CE and the MPU, and for the CE to complete its initial
measurements. The following diagram shows the timing delay of a CE trip indication relative to application of power and the
reference clock.
Power Up Detection Time
The T1 delay is a system parameter dependent on the system clock architecture. T1 could be the start up time for an external
oscillator powered from the same power source as the 71M6403, or T1 could be the delay from a system wide reference clock.
If the reference clock is already stable prior to application of power to the 71M6403 (using a system wide reference clock), the
T1 delay is eliminated. The resultant start up delay reduces to T2 assuming a “clean” application of power to the 71M6403.
71M6403 Power
Reference Clock
CE FAULT_PULSE
CE STROBE
T1
T2
T1: Delay to stable reference clock operation
T2: Delay to CE FAULT_PULSE assertion and
first CE STROBE pulse ( < 5 msec)
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