71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 33 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 45:
Group
0
External interrupt 0
Serial channel 1 interrupt
1
Timer 0 interrupt
-
External interrupt 2
2
External interrupt 1
-
External interrupt 3
3
Timer 1 interrupt
-
External interrupt 4
4
Serial channel 0 interrupt
-
External interrupt 5
5
-
-
External interrupt 6
Table 45: Priority Level Groups
Each group of interrupt sources can be programmed individually to have one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1.
If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 49 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). ZP8 has its own enable and flag
bits in addition to the interrupt 6 enable and flag bits (see Table 44). Note, the ZP8 interrupt must be cleared by the MPU
software.
Interrupt Priority 0 Register (IP0)
MSB LSB
-- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
Table 46: The IP0 Register:
Note: WDTS is not used for interrupt control
Interrupt Priority 1 Register (IP1)
MSB LSB
-
- IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0
Table 47: The IP1 Register:
IP1.x
IP0.x
Priority Level
0 0
Level0
(lowest)
0 1
Level1
1 0
Level2
1 1
Level3
(highest)
Table 48: Priority Levels
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