Teridian 71M6403, Manual

Page: 41 / 75

71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 41 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Internal Clocks and Clock Dividers
All internal clocks are based on CK. This frequency is divided by 4 to generate 4.9152MHz, the frequency supplied to the ADC,
the FIR filter (CKFIR), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU
(CKMPU) and one for the CE (CKCE).
The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2
-MPU_DIV
Hz where
MPU_DIV varies from 0 to 7 ( MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to
38.4kHz. The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM
register
ECK_DIS (0x2005[5]) is asserted by the MPU.
I
2
C Interface (EEPROM)
A dedicated 2-pin serial interface implements an I
2
C driver that can be used to communicate with external EEPROM devices
(type 24C1024). The I
2
C interface can be enabled onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM
register DIO_EEX (0x2008[4]). The MPU communicates with the interface through two SFR registers: EEDATA (0x9E) and
EECTRL (0x9F). If the MPU wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the
‘Transmit’ code to EECTRL . The write to EECTRL initiates the transmit sequence. By observing the BUSY bit in EECTRL the
MPU can determine when the transmit operation is finished (i.e. when the BUSY bit transitions from 1 to 0). INT5 is also
asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission.
A byte is read by writing the ‘Receive’ command to EECTRL and waiting for BUSY to fall. Upon completion, the received data
will appear in EEDATA . The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state
until the next transmission. The bits in EECTRL are shown in Table 56. The EEPROM interface can also be operated by
controlling the DIO4 and DIO5 pins directly.
Note: Clock stretching and multi-master operation is not supported for the I
2
C interface.
Status
Bit
Name
Read/
Write
Polarity Description
7 ERROR R High Asserted when an illegal command is received.
6 BUSY R High Asserted when serial data bus is busy.
5 RX_ACK R High Indicates that the EEPROM sent an ACK bit.
4 TX_ACK R High Indicates when an ACK bit has been sent to the EEPROM
3-0 CMD[3:0] W
See CMD
Table
CMD Operation
0 No-op. Applying the no-op command will stop the
I
2
C clock (SCK, DIO4). Failure to issue the no-op
command will keep the SCK signal toggling.
2 Receive a byte from EEPROM and send ACK.
3 Transmit a byte to EEPROM
5 Issue a ‘STOP’ sequence
6 Receive the last byte from EEPROM and don’t
send ACK.
9 Issue a ‘START’ sequence
Others No Operation, assert ERROR bit
Table 56: EECTRL Status Bits
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