71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 27 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the
watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register
(WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the internal
reset signal becomes active.
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer.
WD Timer Start Procedure:
The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF, an
asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS
is cleared either by the reset signal or by changing the state of the WDT timer.
Refreshing the WD Timer:
The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming
active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and
the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this
period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the
content of the WDTREL register and WDT is automatically reset.
Special Function Registers for the WD Timer
Interrupt Enable 0 Register (IEN0):
MSB
LSB
EAL WDT ET2 ES0 ET1 EX1 ET0 EX0
Table 25: The IEN0 Register
Bit
Symbol
Function
IEN0.6
WDT
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT
is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by
hardware 12 clock cycles after it has been set.
Table 26: The IEN0 Bit Functions
Note: The remaining bits in the IEN0 register are not used for watchdog control
Interrupt Enable 1 Register (IEN1):
MSB
LSB
EXEN2
SWDT EX6 EX5 EX4 EX3 EX2
Table 27: The IEN1 Register
Bit
Symbol
Function
IEN1.6
SWDT
Watchdog timer start/refresh flag.
Set to activate/refresh the watchdog timer. When directly set after setting WDT, a
watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock
cycles after it has been set.
Table 28: The IEN1 Bit Functions
Note: The remaining bits in the IEN1 register are not used for watchdog control
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