71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 12 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
Address
Name
Zero
Reference
Description
0x00
I0
V3P3
Current input 0
0x01
I1
V3P3
Current input 1
0x02
I2
V3P3
Current input 2
0x03
I3
V3P3
Current input 3
0x04
I4
V3P3
Current input 4
0x05
I5
V3P3
Current input 5
0x06 TEMP --- Temperature
0x07
INEUTRAL
VBIAS
INEUTRAL
monitor
Table 2: CE DRAM Locations for ADC Results
CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the six samples taken during
one multiplexer cycle.
The ADC sampling process and resultant accumulation interval calculations are described in the CE Program section.
I1
I3
I2
I5
I4
I0
1/2520.6Hz = 397µs
2/32768Hz =
61.04µs
13/32768Hz = 397µs
per mux cycle
I1
I3
I2
I5
I4
I0
1/2520.6Hz = 397µs
2/32768Hz =
61.04µs
13/32768Hz = 397µs
per mux cycle
Figure 4: Samples in Multiplexer Cycle
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