71M6403
Electronic Trip Unit
SEPTEMBER 2006
Page: 32 of 75
©
2006 TERIDIAN Semiconductor Corporation
REV 1.0
External Interrupts
The external interrupts are connected as shown in Table 43. The polarity of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4 through
6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge
polarity shown in Table 43.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). ZP8 has
its own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44). The ZP8 interrupt must be cleared
by the MPU software. The ZP8 interrupt occurs every 853.4 msec.
External
Interrupt
Connection
Polarity
Flag Reset
0
Digital I/O High Priority
see
DIO_Rx
automatic
1
Digital I/O Low Priority
see
DIO_Rx
automatic
2
Comparator 2 or 3 falling
automatic
3 Reserved
4
Comparator 2 or 3 rising
automatic
5 EEPROM
busy
falling
automatic
6 ZP8
falling
manual
Table 43: External MPU Interrupts
Interrupt 6 is edge-sensitive. The flag for the ZP8 interrupt is located in the
WDI
SFR (address 0xE8).
Enable Bit
Description
Flag Bit
Description
EX0
Enable external interrupt 0
IE0
External interrupt 0 flag
EX1
Enable external interrupt 1
IE1
External interrupt 1 flag
EX2
Enable external interrupt 2
IEX2
External interrupt 2 flag
EX3
Enable external interrupt 3
IEX3
External interrupt 3 flag
EX4
Enable external interrupt 4
IEX4
External interrupt 4 flag
EX5
Enable external interrupt 5
IEX5
External interrupt 5 flag
EX6
Enable external interrupt 6
IEX6
External interrupt 6 flag
EX_ZP8
Enable ZP8 interrupt
IE_ZP8
ZP8 interrupt flag
Table 44: Control Bits for External Interrupts
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